426 lines
7.8 KiB
Plaintext
426 lines
7.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016 BayLibre, Inc.
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*/
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/dts-v1/;
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#include "da850.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "DA850/AM1808/OMAP-L138 LCDK";
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compatible = "ti,da850-lcdk", "ti,da850";
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aliases {
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serial2 = &serial2;
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ethernet0 = ð0;
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};
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chosen {
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stdout-path = "serial2:115200n8";
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};
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memory@c0000000 {
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/* 128 MB DDR2 SDRAM @ 0xc0000000 */
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reg = <0xc0000000 0x08000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dsp_memory_region: dsp-memory@c3000000 {
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compatible = "shared-dma-pool";
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reg = <0xc3000000 0x1000000>;
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reusable;
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status = "okay";
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};
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};
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vcc_5vd: fixedregulator-vcc_5vd {
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compatible = "regulator-fixed";
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regulator-name = "vcc_5vd";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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};
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vcc_3v3d: fixedregulator-vcc_3v3d {
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/* TPS650250 - VDCDC1 */
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compatible = "regulator-fixed";
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regulator-name = "vcc_3v3d";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc_5vd>;
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regulator-always-on;
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regulator-boot-on;
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};
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vcc_1v8d: fixedregulator-vcc_1v8d {
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/* TPS650250 - VDCDC2 */
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compatible = "regulator-fixed";
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regulator-name = "vcc_1v8d";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc_5vd>;
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regulator-always-on;
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regulator-boot-on;
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "DA850-OMAPL138 LCDK";
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simple-audio-card,widgets =
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"Line", "Line In",
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"Line", "Line Out",
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"Microphone", "Mic Jack";
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simple-audio-card,routing =
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"LINE1L", "Line In",
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"LINE1R", "Line In",
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"Line Out", "LLOUT",
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"Line Out", "RLOUT",
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"MIC3L", "Mic Jack",
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"MIC3R", "Mic Jack",
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"Mic Jack", "Mic Bias";
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simple-audio-card,format = "dsp_b";
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simple-audio-card,bitclock-master = <&link0_codec>;
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simple-audio-card,frame-master = <&link0_codec>;
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simple-audio-card,bitclock-inversion;
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simple-audio-card,cpu {
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sound-dai = <&mcasp0>;
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system-clock-frequency = <24576000>;
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};
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link0_codec: simple-audio-card,codec {
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sound-dai = <&tlv320aic3106>;
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system-clock-frequency = <24576000>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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user1 {
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label = "GPIO Key USER1";
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linux,code = <BTN_0>;
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gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
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};
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user2 {
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label = "GPIO Key USER2";
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linux,code = <BTN_1>;
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gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
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};
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};
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vga-bridge {
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compatible = "ti,ths8135";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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vga_bridge_in: endpoint {
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remote-endpoint = <&lcdc_out_vga>;
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};
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};
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port@1 {
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reg = <1>;
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vga_bridge_out: endpoint {
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remote-endpoint = <&vga_con_in>;
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};
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};
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};
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};
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vga {
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compatible = "vga-connector";
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ddc-i2c-bus = <&i2c0>;
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port {
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vga_con_in: endpoint {
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remote-endpoint = <&vga_bridge_out>;
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};
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};
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};
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cvdd: regulator0 {
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compatible = "regulator-fixed";
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regulator-name = "cvdd";
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regulator-min-microvolt = <1300000>;
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regulator-max-microvolt = <1300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&ref_clk {
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clock-frequency = <24000000>;
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};
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&cpu {
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cpu-supply = <&cvdd>;
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};
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/*
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* LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are
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* valid. Unfortunately due to a problem with the DA8XX OHCI controller, we
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* can't enable more than one OPP by default, since the controller sometimes
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* becomes unresponsive after a transition. Fix the frequency at 456 MHz.
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*/
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&opp_100 {
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status = "disabled";
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};
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&opp_200 {
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status = "disabled";
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};
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&opp_300 {
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status = "disabled";
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};
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&opp_456 {
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status = "okay";
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};
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&pmx_core {
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status = "okay";
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mcasp0_pins: pinmux_mcasp0_pins {
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pinctrl-single,bits = <
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/* AHCLKX AFSX ACLKX */
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0x00 0x00101010 0x00f0f0f0
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/* ARX13 ARX14 */
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0x04 0x00000110 0x00000ff0
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>;
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};
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nand_pins: nand_pins {
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pinctrl-single,bits = <
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/* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
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0x1c 0x10110010 0xf0ff00f0
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/*
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* EMA_D[0], EMA_D[1], EMA_D[2],
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* EMA_D[3], EMA_D[4], EMA_D[5],
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* EMA_D[6], EMA_D[7]
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*/
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0x24 0x11111111 0xffffffff
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/*
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* EMA_D[8], EMA_D[9], EMA_D[10],
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* EMA_D[11], EMA_D[12], EMA_D[13],
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* EMA_D[14], EMA_D[15]
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*/
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0x20 0x11111111 0xffffffff
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/* EMA_A[1], EMA_A[2] */
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0x30 0x01100000 0x0ff00000
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>;
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};
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};
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&serial2 {
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pinctrl-names = "default";
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pinctrl-0 = <&serial2_rxtx_pins>;
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status = "okay";
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};
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&wdt {
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status = "okay";
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};
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&rtc0 {
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status = "okay";
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};
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&gpio {
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status = "okay";
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};
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&sata_refclk {
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status = "okay";
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clock-frequency = <100000000>;
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};
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&sata {
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status = "okay";
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};
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&mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins>;
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bus_freq = <2200000>;
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status = "okay";
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};
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ð0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mii_pins>;
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status = "okay";
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};
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&mmc0 {
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max-frequency = <50000000>;
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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clock-frequency = <100000>;
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status = "okay";
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tlv320aic3106: tlv320aic3106@18 {
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#sound-dai-cells = <0>;
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compatible = "ti,tlv320aic3106";
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reg = <0x18>;
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adc-settle-ms = <40>;
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ai3x-micbias-vg = <1>; /* 2.0V */
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status = "okay";
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/* Regulators */
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IOVDD-supply = <&vcc_3v3d>;
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AVDD-supply = <&vcc_3v3d>;
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DRVDD-supply = <&vcc_3v3d>;
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DVDD-supply = <&vcc_1v8d>;
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};
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};
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&mcasp0 {
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#sound-dai-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&mcasp0_pins>;
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status = "okay";
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op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
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tdm-slots = <2>;
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serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
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0 0 0 0
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0 0 0 0
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0 0 0 0
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0 1 2 0
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>;
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tx-num-evt = <32>;
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rx-num-evt = <32>;
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};
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&usb_phy {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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&aemif {
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pinctrl-names = "default";
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pinctrl-0 = <&nand_pins>;
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status = "okay";
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cs3 {
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#address-cells = <2>;
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#size-cells = <1>;
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clock-ranges;
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ranges;
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ti,cs-chipselect = <3>;
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nand@2000000,0 {
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compatible = "ti,davinci-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0 0x02000000 0x02000000
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1 0x00000000 0x00008000>;
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ti,davinci-chipselect = <1>;
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ti,davinci-mask-ale = <0>;
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ti,davinci-mask-cle = <0>;
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ti,davinci-mask-chipsel = <0>;
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ti,davinci-nand-buswidth = <16>;
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ti,davinci-ecc-mode = "hw";
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ti,davinci-ecc-bits = <4>;
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ti,davinci-nand-use-bbt;
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/*
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* The OMAP-L132/L138 Bootloader doc SPRAB41E reads:
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* "To boot from NAND Flash, the AIS should be written
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* to NAND block 1 (NAND block 0 is not used by default)".
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* The same doc mentions that for ROM "Silicon Revision 2.1",
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* "Updated NAND boot mode to offer boot from block 0 or block 1".
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* However the limitaion is left here by default for compatibility
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* with older silicon and because it needs new boot pin settings
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* not possible in stock LCDK.
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*/
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot env";
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reg = <0 0x020000>;
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};
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partition@20000 {
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/* The LCDK defaults to booting from this partition */
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label = "u-boot";
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reg = <0x020000 0x080000>;
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};
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partition@a0000 {
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label = "free space";
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reg = <0x0a0000 0>;
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};
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};
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};
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};
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};
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&prictrl {
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status = "okay";
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};
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&memctrl {
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status = "okay";
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};
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&lcdc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_pins>;
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port {
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lcdc_out_vga: endpoint {
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remote-endpoint = <&vga_bridge_in>;
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};
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};
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};
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&vpif {
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pinctrl-names = "default";
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pinctrl-0 = <&vpif_capture_pins>;
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status = "okay";
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};
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&dsp {
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memory-region = <&dsp_memory_region>;
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status = "okay";
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};
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