1369 lines
31 KiB
Plaintext
1369 lines
31 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mfd/qcom-rpm.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Qualcomm IPQ8064";
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compatible = "qcom,ipq8064";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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};
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cpu1: cpu@1 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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thermal-zones {
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sensor0-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 0>;
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trips {
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cpu-critical {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu-hot {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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sensor1-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 1>;
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trips {
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cpu-critical {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu-hot {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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sensor2-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 2>;
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trips {
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cpu-critical {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu-hot {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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sensor3-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 3>;
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trips {
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cpu-critical {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu-hot {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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sensor4-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 4>;
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trips {
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cpu-critical {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu-hot {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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sensor5-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 5>;
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trips {
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cpu-critical {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu-hot {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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sensor6-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 6>;
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trips {
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cpu-critical {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu-hot {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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sensor7-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 7>;
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trips {
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cpu-critical {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu-hot {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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sensor8-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 8>;
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trips {
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cpu-critical {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu-hot {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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sensor9-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 9>;
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trips {
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cpu-critical {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu-hot {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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sensor10-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsens 10>;
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trips {
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cpu-critical {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "critical";
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};
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cpu-hot {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "hot";
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};
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};
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0>;
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};
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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nss@40000000 {
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reg = <0x40000000 0x1000000>;
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no-map;
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};
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smem: smem@41000000 {
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compatible = "qcom,smem";
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reg = <0x41000000 0x200000>;
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no-map;
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hwlocks = <&sfpb_mutex 3>;
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};
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};
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clocks {
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cxo_board: cxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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pxo_board: pxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-ipq806x", "qcom,scm";
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};
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};
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stmmac_axi_setup: stmmac-axi-config {
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snps,wr_osr_lmt = <7>;
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snps,rd_osr_lmt = <7>;
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snps,blen = <16 0 0 0 0 0 0>;
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};
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vsdcc_fixed: vsdcc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "SDCC Power";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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rpm: rpm@108000 {
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compatible = "qcom,rpm-ipq8064";
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reg = <0x00108000 0x1000>;
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qcom,ipc = <&l2cc 0x8 2>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ack", "err", "wakeup";
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clocks = <&gcc RPM_MSG_RAM_H_CLK>;
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clock-names = "ram";
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rpmcc: clock-controller {
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compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
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#clock-cells = <1>;
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};
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};
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qcom,ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x00500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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};
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qfprom: qfprom@700000 {
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compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
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reg = <0x00700000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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speedbin_efuse: speedbin@c0 {
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reg = <0xc0 0x4>;
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};
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tsens_calib: calib@400 {
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reg = <0x400 0xb>;
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};
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tsens_calib_backup: calib_backup@410 {
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reg = <0x410 0xb>;
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};
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};
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qcom_pinmux: pinmux@800000 {
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compatible = "qcom,ipq8064-pinctrl";
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reg = <0x00800000 0x4000>;
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gpio-controller;
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gpio-ranges = <&qcom_pinmux 0 0 69>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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pcie0_pins: pcie0_pinmux {
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mux {
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pins = "gpio3";
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function = "pcie1_rst";
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drive-strength = <12>;
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bias-disable;
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};
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};
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pcie1_pins: pcie1_pinmux {
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mux {
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pins = "gpio48";
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function = "pcie2_rst";
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drive-strength = <12>;
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bias-disable;
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};
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};
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pcie2_pins: pcie2_pinmux {
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mux {
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pins = "gpio63";
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function = "pcie3_rst";
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drive-strength = <12>;
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bias-disable;
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};
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};
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i2c4_pins: i2c4-default {
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pins = "gpio12", "gpio13";
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function = "gsbi4";
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drive-strength = <12>;
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bias-disable;
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};
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spi_pins: spi_pins {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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function = "gsbi5";
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drive-strength = <10>;
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bias-none;
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};
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};
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leds_pins: leds_pins {
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mux {
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pins = "gpio7", "gpio8", "gpio9",
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"gpio26", "gpio53";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-down;
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output-low;
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};
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};
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buttons_pins: buttons_pins {
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mux {
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pins = "gpio54";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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nand_pins: nand_pins {
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mux {
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pins = "gpio34", "gpio35", "gpio36",
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"gpio37", "gpio38", "gpio39",
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"gpio40", "gpio41", "gpio42",
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"gpio43", "gpio44", "gpio45",
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"gpio46", "gpio47";
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function = "nand";
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drive-strength = <10>;
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bias-disable;
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};
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pullups {
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pins = "gpio39";
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function = "nand";
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drive-strength = <10>;
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bias-pull-up;
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};
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hold {
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pins = "gpio40", "gpio41", "gpio42",
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"gpio43", "gpio44", "gpio45",
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"gpio46", "gpio47";
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function = "nand";
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drive-strength = <10>;
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bias-bus-hold;
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};
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};
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mdio0_pins: mdio0-pins {
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mux {
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pins = "gpio0", "gpio1";
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function = "mdio";
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drive-strength = <8>;
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bias-disable;
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};
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};
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rgmii2_pins: rgmii2-pins {
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mux {
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pins = "gpio27", "gpio28", "gpio29",
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"gpio30", "gpio31", "gpio32",
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"gpio51", "gpio52", "gpio59",
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"gpio60", "gpio61", "gpio62";
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function = "rgmii2";
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drive-strength = <8>;
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bias-disable;
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};
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};
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-ipq8064", "syscon";
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clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
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clock-names = "pxo", "cxo", "pll4";
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reg = <0x00900000 0x4000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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tsens: thermal-sensor@900000 {
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compatible = "qcom,ipq8064-tsens";
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nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
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nvmem-cell-names = "calib", "calib_backup";
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uplow";
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#qcom,sensors = <11>;
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#thermal-sensor-cells = <1>;
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};
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};
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sfpb_mutex: hwlock@1200600 {
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compatible = "qcom,sfpb-mutex";
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reg = <0x01200600 0x100>;
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#hwlock-cells = <1>;
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};
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x02000000 0x1000>,
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<0x02002000 0x1000>;
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};
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timer@200a000 {
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compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer",
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"qcom,msm-timer";
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interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <25000000>;
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clocks = <&sleep_clk>;
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clock-names = "sleep";
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cpu-offset = <0x80000>;
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};
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l2cc: clock-controller@2011000 {
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compatible = "qcom,kpss-gcc", "syscon";
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reg = <0x02011000 0x1000>;
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clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
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clock-names = "pll8_vote", "pxo";
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clock-output-names = "acpu_l2_aux";
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};
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acc0: clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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};
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saw0: regulator@2089000 {
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compatible = "qcom,saw2";
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reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
|
regulator;
|
|
};
|
|
|
|
acc1: clock-controller@2098000 {
|
|
compatible = "qcom,kpss-acc-v1";
|
|
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
|
|
};
|
|
|
|
saw1: regulator@2099000 {
|
|
compatible = "qcom,saw2";
|
|
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
|
|
regulator;
|
|
};
|
|
|
|
nss_common: syscon@03000000 {
|
|
compatible = "syscon";
|
|
reg = <0x03000000 0x0000FFFF>;
|
|
};
|
|
|
|
usb3_0: usb3@100f8800 {
|
|
compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x100f8800 0x8000>;
|
|
clocks = <&gcc USB30_0_MASTER_CLK>;
|
|
clock-names = "core";
|
|
|
|
ranges;
|
|
|
|
resets = <&gcc USB30_0_MASTER_RESET>;
|
|
reset-names = "master";
|
|
|
|
status = "disabled";
|
|
|
|
dwc3_0: dwc3@10000000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x10000000 0xcd00>;
|
|
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&hs_phy_0>, <&ss_phy_0>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
dr_mode = "host";
|
|
snps,dis_u3_susphy_quirk;
|
|
};
|
|
};
|
|
|
|
hs_phy_0: phy@100f8800 {
|
|
compatible = "qcom,ipq806x-usb-phy-hs";
|
|
reg = <0x100f8800 0x30>;
|
|
clocks = <&gcc USB30_0_UTMI_CLK>;
|
|
clock-names = "ref";
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ss_phy_0: phy@100f8830 {
|
|
compatible = "qcom,ipq806x-usb-phy-ss";
|
|
reg = <0x100f8830 0x30>;
|
|
clocks = <&gcc USB30_0_MASTER_CLK>;
|
|
clock-names = "ref";
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3_1: usb3@110f8800 {
|
|
compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x110f8800 0x8000>;
|
|
clocks = <&gcc USB30_1_MASTER_CLK>;
|
|
clock-names = "core";
|
|
|
|
ranges;
|
|
|
|
resets = <&gcc USB30_1_MASTER_RESET>;
|
|
reset-names = "master";
|
|
|
|
status = "disabled";
|
|
|
|
dwc3_1: dwc3@11000000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x11000000 0xcd00>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&hs_phy_1>, <&ss_phy_1>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
dr_mode = "host";
|
|
snps,dis_u3_susphy_quirk;
|
|
};
|
|
};
|
|
|
|
hs_phy_1: phy@110f8800 {
|
|
compatible = "qcom,ipq806x-usb-phy-hs";
|
|
reg = <0x110f8800 0x30>;
|
|
clocks = <&gcc USB30_1_UTMI_CLK>;
|
|
clock-names = "ref";
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ss_phy_1: phy@110f8830 {
|
|
compatible = "qcom,ipq806x-usb-phy-ss";
|
|
reg = <0x110f8830 0x30>;
|
|
clocks = <&gcc USB30_1_MASTER_CLK>;
|
|
clock-names = "ref";
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
sdcc3bam: dma-controller@12182000 {
|
|
compatible = "qcom,bam-v1.3.0";
|
|
reg = <0x12182000 0x8000>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc SDC3_H_CLK>;
|
|
clock-names = "bam_clk";
|
|
#dma-cells = <1>;
|
|
qcom,ee = <0>;
|
|
};
|
|
|
|
sdcc1bam: dma-controller@12402000 {
|
|
compatible = "qcom,bam-v1.3.0";
|
|
reg = <0x12402000 0x8000>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc SDC1_H_CLK>;
|
|
clock-names = "bam_clk";
|
|
#dma-cells = <1>;
|
|
qcom,ee = <0>;
|
|
};
|
|
|
|
amba: amba {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
sdcc3: mmc@12180000 {
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
arm,primecell-periphid = <0x00051180>;
|
|
status = "disabled";
|
|
reg = <0x12180000 0x2000>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
bus-width = <8>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
max-frequency = <192000000>;
|
|
sd-uhs-sdr104;
|
|
sd-uhs-ddr50;
|
|
vqmmc-supply = <&vsdcc_fixed>;
|
|
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
sdcc1: mmc@12400000 {
|
|
status = "disabled";
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
arm,primecell-periphid = <0x00051180>;
|
|
reg = <0x12400000 0x2000>;
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
bus-width = <8>;
|
|
max-frequency = <96000000>;
|
|
non-removable;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
vmmc-supply = <&vsdcc_fixed>;
|
|
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
};
|
|
|
|
gsbi1: gsbi@12440000 {
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
reg = <0x12440000 0x100>;
|
|
cell-index = <1>;
|
|
clocks = <&gcc GSBI1_H_CLK>;
|
|
clock-names = "iface";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
status = "disabled";
|
|
|
|
gsbi1_serial: serial@12450000 {
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
reg = <0x12450000 0x100>,
|
|
<0x12400000 0x03>;
|
|
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gsbi1_i2c: i2c@12460000 {
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
reg = <0x12460000 0x1000>;
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gsbi2: gsbi@12480000 {
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
cell-index = <2>;
|
|
reg = <0x12480000 0x100>;
|
|
clocks = <&gcc GSBI2_H_CLK>;
|
|
clock-names = "iface";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
gsbi2_serial: serial@12490000 {
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
reg = <0x12490000 0x1000>,
|
|
<0x12480000 0x1000>;
|
|
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
gsbi2_i2c: i2c@124a0000 {
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
reg = <0x124a0000 0x1000>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
gsbi4: gsbi@16300000 {
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
cell-index = <4>;
|
|
reg = <0x16300000 0x100>;
|
|
clocks = <&gcc GSBI4_H_CLK>;
|
|
clock-names = "iface";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
gsbi4_serial: serial@16340000 {
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
reg = <0x16340000 0x1000>,
|
|
<0x16300000 0x1000>;
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@16380000 {
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
reg = <0x16380000 0x1000>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
gsbi6: gsbi@16500000 {
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
reg = <0x16500000 0x100>;
|
|
cell-index = <6>;
|
|
clocks = <&gcc GSBI6_H_CLK>;
|
|
clock-names = "iface";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
status = "disabled";
|
|
|
|
gsbi6_i2c: i2c@16580000 {
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
reg = <0x16580000 0x1000>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gsbi6_spi: spi@16580000 {
|
|
compatible = "qcom,spi-qup-v1.1.1";
|
|
reg = <0x16580000 0x1000>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gsbi7: gsbi@16600000 {
|
|
status = "disabled";
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
cell-index = <7>;
|
|
reg = <0x16600000 0x100>;
|
|
clocks = <&gcc GSBI7_H_CLK>;
|
|
clock-names = "iface";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
gsbi7_serial: serial@16640000 {
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
reg = <0x16640000 0x1000>,
|
|
<0x16600000 0x1000>;
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
gsbi7_i2c: i2c@16680000 {
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
reg = <0x16680000 0x1000>;
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
adm_dma: dma-controller@18300000 {
|
|
compatible = "qcom,adm";
|
|
reg = <0x18300000 0x100000>;
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
|
|
clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
|
|
clock-names = "core", "iface";
|
|
|
|
resets = <&gcc ADM0_RESET>,
|
|
<&gcc ADM0_PBUS_RESET>,
|
|
<&gcc ADM0_C0_RESET>,
|
|
<&gcc ADM0_C1_RESET>,
|
|
<&gcc ADM0_C2_RESET>;
|
|
reset-names = "clk", "pbus", "c0", "c1", "c2";
|
|
qcom,ee = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gsbi5: gsbi@1a200000 {
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
cell-index = <5>;
|
|
reg = <0x1a200000 0x100>;
|
|
clocks = <&gcc GSBI5_H_CLK>;
|
|
clock-names = "iface";
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
gsbi5_serial: serial@1a240000 {
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
reg = <0x1a240000 0x1000>,
|
|
<0x1a200000 0x1000>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@1a280000 {
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
reg = <0x1a280000 0x1000>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
spi@1a280000 {
|
|
compatible = "qcom,spi-qup-v1.1.1";
|
|
reg = <0x1a280000 0x1000>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
tcsr: syscon@1a400000 {
|
|
compatible = "qcom,tcsr-ipq8064", "syscon";
|
|
reg = <0x1a400000 0x100>;
|
|
};
|
|
|
|
rng@1a500000 {
|
|
compatible = "qcom,prng";
|
|
reg = <0x1a500000 0x200>;
|
|
clocks = <&gcc PRNG_CLK>;
|
|
clock-names = "core";
|
|
};
|
|
|
|
nand: nand-controller@1ac00000 {
|
|
compatible = "qcom,ipq806x-nand";
|
|
reg = <0x1ac00000 0x800>;
|
|
|
|
pinctrl-0 = <&nand_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
clocks = <&gcc EBI2_CLK>,
|
|
<&gcc EBI2_AON_CLK>;
|
|
clock-names = "core", "aon";
|
|
|
|
dmas = <&adm_dma 3>;
|
|
dma-names = "rxtx";
|
|
qcom,cmd-crci = <15>;
|
|
qcom,data-crci = <3>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
sata_phy: sata-phy@1b400000 {
|
|
compatible = "qcom,ipq806x-sata-phy";
|
|
reg = <0x1b400000 0x200>;
|
|
|
|
clocks = <&gcc SATA_PHY_CFG_CLK>;
|
|
clock-names = "cfg";
|
|
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie0: pci@1b500000 {
|
|
compatible = "qcom,pcie-ipq8064";
|
|
reg = <0x1b500000 0x1000
|
|
0x1b502000 0x80
|
|
0x1b600000 0x100
|
|
0x0ff00000 0x100000>;
|
|
reg-names = "dbi", "elbi", "parf", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */
|
|
0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */
|
|
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
clocks = <&gcc PCIE_A_CLK>,
|
|
<&gcc PCIE_H_CLK>,
|
|
<&gcc PCIE_PHY_CLK>,
|
|
<&gcc PCIE_AUX_CLK>,
|
|
<&gcc PCIE_ALT_REF_CLK>;
|
|
clock-names = "core", "iface", "phy", "aux", "ref";
|
|
|
|
assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc PCIE_ACLK_RESET>,
|
|
<&gcc PCIE_HCLK_RESET>,
|
|
<&gcc PCIE_POR_RESET>,
|
|
<&gcc PCIE_PCI_RESET>,
|
|
<&gcc PCIE_PHY_RESET>,
|
|
<&gcc PCIE_EXT_RESET>;
|
|
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
|
|
|
pinctrl-0 = <&pcie0_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "disabled";
|
|
perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
pcie1: pci@1b700000 {
|
|
compatible = "qcom,pcie-ipq8064";
|
|
reg = <0x1b700000 0x1000
|
|
0x1b702000 0x80
|
|
0x1b800000 0x100
|
|
0x31f00000 0x100000>;
|
|
reg-names = "dbi", "elbi", "parf", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <1>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */
|
|
0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */
|
|
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
clocks = <&gcc PCIE_1_A_CLK>,
|
|
<&gcc PCIE_1_H_CLK>,
|
|
<&gcc PCIE_1_PHY_CLK>,
|
|
<&gcc PCIE_1_AUX_CLK>,
|
|
<&gcc PCIE_1_ALT_REF_CLK>;
|
|
clock-names = "core", "iface", "phy", "aux", "ref";
|
|
|
|
assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc PCIE_1_ACLK_RESET>,
|
|
<&gcc PCIE_1_HCLK_RESET>,
|
|
<&gcc PCIE_1_POR_RESET>,
|
|
<&gcc PCIE_1_PCI_RESET>,
|
|
<&gcc PCIE_1_PHY_RESET>,
|
|
<&gcc PCIE_1_EXT_RESET>;
|
|
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
|
|
|
pinctrl-0 = <&pcie1_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "disabled";
|
|
perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
pcie2: pci@1b900000 {
|
|
compatible = "qcom,pcie-ipq8064";
|
|
reg = <0x1b900000 0x1000
|
|
0x1b902000 0x80
|
|
0x1ba00000 0x100
|
|
0x35f00000 0x100000>;
|
|
reg-names = "dbi", "elbi", "parf", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <2>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */
|
|
0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */
|
|
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
clocks = <&gcc PCIE_2_A_CLK>,
|
|
<&gcc PCIE_2_H_CLK>,
|
|
<&gcc PCIE_2_PHY_CLK>,
|
|
<&gcc PCIE_2_AUX_CLK>,
|
|
<&gcc PCIE_2_ALT_REF_CLK>;
|
|
clock-names = "core", "iface", "phy", "aux", "ref";
|
|
|
|
assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc PCIE_2_ACLK_RESET>,
|
|
<&gcc PCIE_2_HCLK_RESET>,
|
|
<&gcc PCIE_2_POR_RESET>,
|
|
<&gcc PCIE_2_PCI_RESET>,
|
|
<&gcc PCIE_2_PHY_RESET>,
|
|
<&gcc PCIE_2_EXT_RESET>;
|
|
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
|
|
|
pinctrl-0 = <&pcie2_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "disabled";
|
|
perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
qsgmii_csr: syscon@1bb00000 {
|
|
compatible = "syscon";
|
|
reg = <0x1bb00000 0x000001FF>;
|
|
};
|
|
|
|
lcc: clock-controller@28000000 {
|
|
compatible = "qcom,lcc-ipq8064";
|
|
reg = <0x28000000 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
lpass@28100000 {
|
|
compatible = "qcom,lpass-cpu";
|
|
status = "disabled";
|
|
clocks = <&lcc AHBIX_CLK>,
|
|
<&lcc MI2S_OSR_CLK>,
|
|
<&lcc MI2S_BIT_CLK>;
|
|
clock-names = "ahbix-clk",
|
|
"mi2s-osr-clk",
|
|
"mi2s-bit-clk";
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "lpass-irq-lpaif";
|
|
reg = <0x28100000 0x10000>;
|
|
reg-names = "lpass-lpaif";
|
|
};
|
|
|
|
sata: sata@29000000 {
|
|
compatible = "qcom,ipq806x-ahci", "generic-ahci";
|
|
reg = <0x29000000 0x180>;
|
|
|
|
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc SFAB_SATA_S_H_CLK>,
|
|
<&gcc SATA_H_CLK>,
|
|
<&gcc SATA_A_CLK>,
|
|
<&gcc SATA_RXOOB_CLK>,
|
|
<&gcc SATA_PMALIVE_CLK>;
|
|
clock-names = "slave_face", "iface", "core",
|
|
"rxoob", "pmalive";
|
|
|
|
assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
|
|
assigned-clock-rates = <100000000>, <100000000>;
|
|
|
|
phys = <&sata_phy>;
|
|
phy-names = "sata-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac0: ethernet@37000000 {
|
|
device_type = "network";
|
|
compatible = "qcom,ipq806x-gmac", "snps,dwmac";
|
|
reg = <0x37000000 0x200000>;
|
|
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
|
|
snps,axi-config = <&stmmac_axi_setup>;
|
|
snps,pbl = <32>;
|
|
snps,aal;
|
|
|
|
qcom,nss-common = <&nss_common>;
|
|
qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
|
|
clocks = <&gcc GMAC_CORE1_CLK>;
|
|
clock-names = "stmmaceth";
|
|
|
|
resets = <&gcc GMAC_CORE1_RESET>,
|
|
<&gcc GMAC_AHB_RESET>;
|
|
reset-names = "stmmaceth", "ahb";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac1: ethernet@37200000 {
|
|
device_type = "network";
|
|
compatible = "qcom,ipq806x-gmac", "snps,dwmac";
|
|
reg = <0x37200000 0x200000>;
|
|
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
|
|
snps,axi-config = <&stmmac_axi_setup>;
|
|
snps,pbl = <32>;
|
|
snps,aal;
|
|
|
|
qcom,nss-common = <&nss_common>;
|
|
qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
|
|
clocks = <&gcc GMAC_CORE2_CLK>;
|
|
clock-names = "stmmaceth";
|
|
|
|
resets = <&gcc GMAC_CORE2_RESET>,
|
|
<&gcc GMAC_AHB_RESET>;
|
|
reset-names = "stmmaceth", "ahb";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac2: ethernet@37400000 {
|
|
device_type = "network";
|
|
compatible = "qcom,ipq806x-gmac", "snps,dwmac";
|
|
reg = <0x37400000 0x200000>;
|
|
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
|
|
snps,axi-config = <&stmmac_axi_setup>;
|
|
snps,pbl = <32>;
|
|
snps,aal;
|
|
|
|
qcom,nss-common = <&nss_common>;
|
|
qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
|
|
clocks = <&gcc GMAC_CORE3_CLK>;
|
|
clock-names = "stmmaceth";
|
|
|
|
resets = <&gcc GMAC_CORE3_RESET>,
|
|
<&gcc GMAC_AHB_RESET>;
|
|
reset-names = "stmmaceth", "ahb";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac3: ethernet@37600000 {
|
|
device_type = "network";
|
|
compatible = "qcom,ipq806x-gmac", "snps,dwmac";
|
|
reg = <0x37600000 0x200000>;
|
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
|
|
snps,axi-config = <&stmmac_axi_setup>;
|
|
snps,pbl = <32>;
|
|
snps,aal;
|
|
|
|
qcom,nss-common = <&nss_common>;
|
|
qcom,qsgmii-csr = <&qsgmii_csr>;
|
|
|
|
clocks = <&gcc GMAC_CORE4_CLK>;
|
|
clock-names = "stmmaceth";
|
|
|
|
resets = <&gcc GMAC_CORE4_RESET>,
|
|
<&gcc GMAC_AHB_RESET>;
|
|
reset-names = "stmmaceth", "ahb";
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|