133 lines
5.5 KiB
C
133 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This contains hardware definitions that are common between i.MX21 and
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* i.MX27.
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*/
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#ifndef __MACH_MX2x_H__
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#define __MACH_MX2x_H__
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/* The following addresses are common between i.MX21 and i.MX27 */
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/* Register offsets */
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#define MX2x_AIPI_BASE_ADDR 0x10000000
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#define MX2x_AIPI_SIZE SZ_1M
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#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
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#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
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#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
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#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
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#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
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#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
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#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
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#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
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#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
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#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
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#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
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#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
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#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
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#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
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#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
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#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
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#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
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#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
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#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
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#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
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#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
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#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
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#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
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#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
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#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
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#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
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#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
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#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
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#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
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#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
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#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
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#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
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#define MX2x_AVIC_BASE_ADDR 0x10040000
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#define MX2x_SAHB1_BASE_ADDR 0x80000000
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#define MX2x_SAHB1_SIZE SZ_1M
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#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
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/* fixed interrupt numbers */
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#include <asm/irq.h>
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#define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)
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#define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)
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#define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)
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#define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)
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#define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)
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#define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)
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#define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)
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#define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)
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#define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)
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#define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)
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#define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18)
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#define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19)
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#define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20)
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#define MX2x_INT_KPP (NR_IRQS_LEGACY + 21)
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#define MX2x_INT_RTC (NR_IRQS_LEGACY + 22)
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#define MX2x_INT_PWM (NR_IRQS_LEGACY + 23)
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#define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24)
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#define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25)
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#define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26)
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#define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27)
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#define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28)
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#define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29)
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#define MX2x_INT_CSI (NR_IRQS_LEGACY + 31)
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#define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32)
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#define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33)
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#define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34)
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#define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35)
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#define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36)
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#define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37)
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#define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38)
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#define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39)
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#define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40)
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#define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41)
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#define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42)
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#define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43)
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#define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44)
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#define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45)
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#define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46)
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#define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47)
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#define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
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#define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52)
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#define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60)
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#define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61)
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/* fixed DMA request numbers */
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#define MX2x_DMA_REQ_CSPI3_RX 1
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#define MX2x_DMA_REQ_CSPI3_TX 2
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#define MX2x_DMA_REQ_EXT 3
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#define MX2x_DMA_REQ_SDHC2 6
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#define MX2x_DMA_REQ_SDHC1 7
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#define MX2x_DMA_REQ_SSI2_RX0 8
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#define MX2x_DMA_REQ_SSI2_TX0 9
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#define MX2x_DMA_REQ_SSI2_RX1 10
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#define MX2x_DMA_REQ_SSI2_TX1 11
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#define MX2x_DMA_REQ_SSI1_RX0 12
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#define MX2x_DMA_REQ_SSI1_TX0 13
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#define MX2x_DMA_REQ_SSI1_RX1 14
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#define MX2x_DMA_REQ_SSI1_TX1 15
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#define MX2x_DMA_REQ_CSPI2_RX 16
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#define MX2x_DMA_REQ_CSPI2_TX 17
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#define MX2x_DMA_REQ_CSPI1_RX 18
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#define MX2x_DMA_REQ_CSPI1_TX 19
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#define MX2x_DMA_REQ_UART4_RX 20
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#define MX2x_DMA_REQ_UART4_TX 21
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#define MX2x_DMA_REQ_UART3_RX 22
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#define MX2x_DMA_REQ_UART3_TX 23
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#define MX2x_DMA_REQ_UART2_RX 24
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#define MX2x_DMA_REQ_UART2_TX 25
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#define MX2x_DMA_REQ_UART1_RX 26
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#define MX2x_DMA_REQ_UART1_TX 27
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#define MX2x_DMA_REQ_CSI_STAT 30
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#define MX2x_DMA_REQ_CSI_RX 31
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#endif /* ifndef __MACH_MX2x_H__ */
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