481 lines
10 KiB
C
481 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Copyright 2012 Linaro Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/clk/mxs.h>
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#include <linux/clkdev.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/irqchip/mxs.h>
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#include <linux/reboot.h>
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#include <linux/micrel_phy.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/phy.h>
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#include <linux/sys_soc.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/system_info.h>
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#include <asm/system_misc.h>
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#include "pm.h"
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/* MXS DIGCTL SAIF CLKMUX */
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#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0
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#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1
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#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2
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#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3
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#define HW_DIGCTL_CHIPID 0x310
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#define HW_DIGCTL_CHIPID_MASK (0xffff << 16)
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#define HW_DIGCTL_REV_MASK 0xff
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#define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16)
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#define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16)
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#define MXS_CHIP_REVISION_1_0 0x10
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#define MXS_CHIP_REVISION_1_1 0x11
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#define MXS_CHIP_REVISION_1_2 0x12
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#define MXS_CHIP_REVISION_1_3 0x13
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#define MXS_CHIP_REVISION_1_4 0x14
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#define MXS_CHIP_REV_UNKNOWN 0xff
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#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
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#define MXS_SET_ADDR 0x4
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#define MXS_CLR_ADDR 0x8
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#define MXS_TOG_ADDR 0xc
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#define HW_OCOTP_OPS2 19 /* offset 0x150 */
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#define HW_OCOTP_OPS3 20 /* offset 0x160 */
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static u32 chipid;
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static u32 socid;
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static void __iomem *reset_addr;
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static inline void __mxs_setl(u32 mask, void __iomem *reg)
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{
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__raw_writel(mask, reg + MXS_SET_ADDR);
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}
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static inline void __mxs_clrl(u32 mask, void __iomem *reg)
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{
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__raw_writel(mask, reg + MXS_CLR_ADDR);
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}
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static inline void __mxs_togl(u32 mask, void __iomem *reg)
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{
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__raw_writel(mask, reg + MXS_TOG_ADDR);
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}
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#define OCOTP_WORD_OFFSET 0x20
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#define OCOTP_WORD_COUNT 0x20
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#define BM_OCOTP_CTRL_BUSY (1 << 8)
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#define BM_OCOTP_CTRL_ERROR (1 << 9)
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#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
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static DEFINE_MUTEX(ocotp_mutex);
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static u32 ocotp_words[OCOTP_WORD_COUNT];
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static const u32 *mxs_get_ocotp(void)
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{
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struct device_node *np;
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void __iomem *ocotp_base;
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int timeout = 0x400;
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size_t i;
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static int once;
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if (once)
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return ocotp_words;
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np = of_find_compatible_node(NULL, NULL, "fsl,ocotp");
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ocotp_base = of_iomap(np, 0);
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WARN_ON(!ocotp_base);
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mutex_lock(&ocotp_mutex);
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/*
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* clk_enable(hbus_clk) for ocotp can be skipped
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* as it must be on when system is running.
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*/
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/* try to clear ERROR bit */
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__mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
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/* check both BUSY and ERROR cleared */
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while ((__raw_readl(ocotp_base) &
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(BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
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cpu_relax();
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if (unlikely(!timeout))
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goto error_unlock;
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/* open OCOTP banks for read */
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__mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
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/* approximately wait 32 hclk cycles */
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udelay(1);
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/* poll BUSY bit becoming cleared */
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timeout = 0x400;
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while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
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cpu_relax();
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if (unlikely(!timeout))
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goto error_unlock;
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for (i = 0; i < OCOTP_WORD_COUNT; i++)
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ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
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i * 0x10);
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/* close banks for power saving */
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__mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
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once = 1;
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mutex_unlock(&ocotp_mutex);
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return ocotp_words;
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error_unlock:
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mutex_unlock(&ocotp_mutex);
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pr_err("%s: timeout in reading OCOTP\n", __func__);
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return NULL;
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}
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enum mac_oui {
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OUI_FSL,
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OUI_DENX,
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OUI_CRYSTALFONTZ,
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OUI_I2SE,
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OUI_ARMADEUS,
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};
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static void __init update_fec_mac_prop(enum mac_oui oui)
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{
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struct device_node *np, *from = NULL;
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struct property *newmac;
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const u32 *ocotp = mxs_get_ocotp();
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u8 *macaddr;
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u32 val;
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int i;
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for (i = 0; i < 2; i++) {
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np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
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if (!np)
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return;
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from = np;
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if (of_get_property(np, "local-mac-address", NULL))
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continue;
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newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
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if (!newmac)
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return;
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newmac->value = newmac + 1;
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newmac->length = 6;
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newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
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if (!newmac->name) {
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kfree(newmac);
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return;
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}
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/*
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* OCOTP only stores the last 4 octets for each mac address,
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* so hard-code OUI here.
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*/
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macaddr = newmac->value;
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switch (oui) {
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case OUI_FSL:
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macaddr[0] = 0x00;
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macaddr[1] = 0x04;
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macaddr[2] = 0x9f;
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break;
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case OUI_DENX:
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macaddr[0] = 0xc0;
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macaddr[1] = 0xe5;
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macaddr[2] = 0x4e;
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break;
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case OUI_CRYSTALFONTZ:
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macaddr[0] = 0x58;
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macaddr[1] = 0xb9;
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macaddr[2] = 0xe1;
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break;
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case OUI_I2SE:
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macaddr[0] = 0x00;
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macaddr[1] = 0x01;
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macaddr[2] = 0x87;
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break;
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case OUI_ARMADEUS:
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macaddr[0] = 0x00;
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macaddr[1] = 0x1e;
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macaddr[2] = 0xac;
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break;
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}
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val = ocotp[i];
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macaddr[3] = (val >> 16) & 0xff;
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macaddr[4] = (val >> 8) & 0xff;
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macaddr[5] = (val >> 0) & 0xff;
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of_update_property(np, newmac);
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}
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}
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static inline void enable_clk_enet_out(void)
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{
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struct clk *clk = clk_get_sys("enet_out", NULL);
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if (!IS_ERR(clk))
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clk_prepare_enable(clk);
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}
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static void __init imx28_evk_init(void)
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{
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update_fec_mac_prop(OUI_FSL);
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mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
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}
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static void __init imx28_apf28_init(void)
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{
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update_fec_mac_prop(OUI_ARMADEUS);
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}
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static int apx4devkit_phy_fixup(struct phy_device *phy)
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{
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phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
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return 0;
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}
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static void __init apx4devkit_init(void)
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{
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enable_clk_enet_out();
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if (IS_BUILTIN(CONFIG_PHYLIB))
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phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
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apx4devkit_phy_fixup);
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}
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static void __init crystalfontz_init(void)
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{
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update_fec_mac_prop(OUI_CRYSTALFONTZ);
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}
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static void __init duckbill_init(void)
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{
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update_fec_mac_prop(OUI_I2SE);
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}
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static void __init m28cu3_init(void)
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{
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update_fec_mac_prop(OUI_DENX);
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}
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static const char __init *mxs_get_soc_id(void)
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{
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struct device_node *np;
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void __iomem *digctl_base;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
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digctl_base = of_iomap(np, 0);
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WARN_ON(!digctl_base);
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chipid = readl(digctl_base + HW_DIGCTL_CHIPID);
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socid = chipid & HW_DIGCTL_CHIPID_MASK;
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iounmap(digctl_base);
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of_node_put(np);
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switch (socid) {
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case HW_DIGCTL_CHIPID_MX23:
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return "i.MX23";
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case HW_DIGCTL_CHIPID_MX28:
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return "i.MX28";
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default:
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return "Unknown";
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}
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}
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static u32 __init mxs_get_cpu_rev(void)
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{
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u32 rev = chipid & HW_DIGCTL_REV_MASK;
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switch (socid) {
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case HW_DIGCTL_CHIPID_MX23:
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switch (rev) {
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case 0x0:
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return MXS_CHIP_REVISION_1_0;
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case 0x1:
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return MXS_CHIP_REVISION_1_1;
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case 0x2:
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return MXS_CHIP_REVISION_1_2;
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case 0x3:
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return MXS_CHIP_REVISION_1_3;
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case 0x4:
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return MXS_CHIP_REVISION_1_4;
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default:
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return MXS_CHIP_REV_UNKNOWN;
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}
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case HW_DIGCTL_CHIPID_MX28:
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switch (rev) {
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case 0x0:
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return MXS_CHIP_REVISION_1_1;
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case 0x1:
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return MXS_CHIP_REVISION_1_2;
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default:
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return MXS_CHIP_REV_UNKNOWN;
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}
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default:
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return MXS_CHIP_REV_UNKNOWN;
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}
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}
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static const char __init *mxs_get_revision(void)
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{
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u32 rev = mxs_get_cpu_rev();
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if (rev != MXS_CHIP_REV_UNKNOWN)
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return kasprintf(GFP_KERNEL, "%d.%d", (rev >> 4) & 0xf,
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rev & 0xf);
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else
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return kasprintf(GFP_KERNEL, "%s", "Unknown");
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}
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#define MX23_CLKCTRL_RESET_OFFSET 0x120
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#define MX28_CLKCTRL_RESET_OFFSET 0x1e0
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static int __init mxs_restart_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
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reset_addr = of_iomap(np, 0);
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if (!reset_addr)
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return -ENODEV;
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if (of_device_is_compatible(np, "fsl,imx23-clkctrl"))
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reset_addr += MX23_CLKCTRL_RESET_OFFSET;
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else
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reset_addr += MX28_CLKCTRL_RESET_OFFSET;
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of_node_put(np);
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return 0;
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}
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static void __init eukrea_mbmx283lc_init(void)
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{
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mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
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}
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static void __init mxs_machine_init(void)
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{
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struct device_node *root;
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struct device *parent;
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struct soc_device *soc_dev;
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struct soc_device_attribute *soc_dev_attr;
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u64 soc_uid = 0;
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const u32 *ocotp = mxs_get_ocotp();
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int ret;
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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return;
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root = of_find_node_by_path("/");
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ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
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if (ret) {
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kfree(soc_dev_attr);
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return;
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}
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soc_dev_attr->family = "Freescale MXS Family";
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soc_dev_attr->soc_id = mxs_get_soc_id();
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soc_dev_attr->revision = mxs_get_revision();
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if (socid == HW_DIGCTL_CHIPID_MX23) {
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soc_uid = system_serial_low = ocotp[HW_OCOTP_OPS3];
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} else if (socid == HW_DIGCTL_CHIPID_MX28) {
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soc_uid = system_serial_high = ocotp[HW_OCOTP_OPS2];
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soc_uid <<= 32;
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system_serial_low = ocotp[HW_OCOTP_OPS3];
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soc_uid |= system_serial_low;
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}
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if (soc_uid)
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soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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kfree(soc_dev_attr->serial_number);
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kfree(soc_dev_attr->revision);
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kfree(soc_dev_attr);
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return;
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}
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parent = soc_device_to_device(soc_dev);
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if (of_machine_is_compatible("fsl,imx28-evk"))
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imx28_evk_init();
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if (of_machine_is_compatible("armadeus,imx28-apf28"))
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imx28_apf28_init();
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else if (of_machine_is_compatible("bluegiga,apx4devkit"))
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apx4devkit_init();
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else if (of_machine_is_compatible("crystalfontz,cfa10036"))
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crystalfontz_init();
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else if (of_machine_is_compatible("eukrea,mbmx283lc"))
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eukrea_mbmx283lc_init();
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else if (of_machine_is_compatible("i2se,duckbill") ||
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of_machine_is_compatible("i2se,duckbill-2"))
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duckbill_init();
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else if (of_machine_is_compatible("msr,m28cu3"))
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m28cu3_init();
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of_platform_default_populate(NULL, NULL, parent);
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mxs_restart_init();
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}
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#define MXS_CLKCTRL_RESET_CHIP (1 << 1)
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/*
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* Reset the system. It is called by machine_restart().
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*/
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static void mxs_restart(enum reboot_mode mode, const char *cmd)
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{
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if (reset_addr) {
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/* reset the chip */
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__mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
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pr_err("Failed to assert the chip reset\n");
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/* Delay to allow the serial port to show the message */
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mdelay(50);
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}
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/* We'll take a jump through zero as a poor second */
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soft_restart(0);
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}
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static const char *const mxs_dt_compat[] __initconst = {
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"fsl,imx28",
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"fsl,imx23",
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NULL,
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};
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DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
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.handle_irq = icoll_handle_irq,
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.init_machine = mxs_machine_init,
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.init_late = mxs_pm_init,
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.dt_compat = mxs_dt_compat,
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.restart = mxs_restart,
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MACHINE_END
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