1135 lines
25 KiB
Plaintext
1135 lines
25 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2020 Gateworks Corporation
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/linux-event-codes.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include "imx8mm.dtsi"
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/ {
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model = "Gateworks Venice GW7901 i.MX8MM board";
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compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
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aliases {
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ethernet0 = &fec1;
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ethernet1 = &lan1;
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ethernet2 = &lan2;
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ethernet3 = &lan3;
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ethernet4 = &lan4;
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usb0 = &usbotg1;
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usb1 = &usbotg2;
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};
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chosen {
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stdout-path = &uart2;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0x80000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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key-user-pb {
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label = "user_pb";
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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key-user-pb1x {
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label = "user_pb1x";
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linux,code = <BTN_1>;
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interrupt-parent = <&gsc>;
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interrupts = <0>;
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};
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key-erased {
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label = "key_erased";
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linux,code = <BTN_2>;
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interrupt-parent = <&gsc>;
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interrupts = <1>;
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};
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key-eeprom-wp {
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label = "eeprom_wp";
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linux,code = <BTN_3>;
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interrupt-parent = <&gsc>;
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interrupts = <2>;
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};
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key-tamper {
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label = "tamper";
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linux,code = <BTN_4>;
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interrupt-parent = <&gsc>;
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interrupts = <5>;
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};
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switch-hold {
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label = "switch_hold";
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linux,code = <BTN_5>;
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interrupt-parent = <&gsc>;
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interrupts = <7>;
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};
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};
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led-controller {
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compatible = "gpio-leds";
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led-0 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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label = "led01_red";
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gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-1 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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label = "led01_grn";
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gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-2 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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label = "led02_red";
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gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-3 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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label = "led02_grn";
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gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-4 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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label = "led03_red";
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gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-5 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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label = "led03_grn";
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gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-6 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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label = "led04_red";
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gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-7 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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label = "led04_grn";
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gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-8 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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label = "led05_red";
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gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-9 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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label = "led05_grn";
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gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-a {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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label = "led06_red";
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gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-b {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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label = "led06_grn";
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gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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pcie0_refclk: pcie0-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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regulator-ioexp {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_ioexp>;
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compatible = "regulator-fixed";
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regulator-name = "ioexp";
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gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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regulator-isouart {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_isouart>;
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compatible = "regulator-fixed";
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regulator-name = "iso_uart";
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gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
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startup-delay-us = <100>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_usb2_vbus: regulator-usb2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usb2>;
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compatible = "regulator-fixed";
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regulator-name = "usb_usb2_vbus";
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gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_wifi: regulator-wifi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_wl>;
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compatible = "regulator-fixed";
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regulator-name = "wifi";
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gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&ddrc {
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operating-points-v2 = <&ddrc_opp_table>;
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ddrc_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-25000000 {
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opp-hz = /bits/ 64 <25000000>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-750000000 {
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opp-hz = /bits/ 64 <750000000>;
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};
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};
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};
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&disp_blk_ctrl {
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status = "disabled";
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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status = "okay";
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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local-mac-address = [00 00 00 00 00 00];
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&gpio1 {
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gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#",
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"", "uart1_rs232#", "dig1_in", "dig1_out",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&gpio4 {
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gpio-line-names = "", "", "", "",
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"", "", "uart3_rs232#", "uart3_rs422#",
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"uart3_rs485#", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
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};
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&gpio5 {
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gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "",
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"", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&gpu_2d {
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status = "disabled";
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};
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&gpu_3d {
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status = "disabled";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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gsc: gsc@20 {
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compatible = "gw,gsc";
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reg = <0x20>;
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pinctrl-0 = <&pinctrl_gsc>;
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interrupt-parent = <&gpio4>;
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interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <1>;
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adc {
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compatible = "gw,gsc-adc";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@6 {
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gw,mode = <0>;
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reg = <0x06>;
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label = "temp";
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};
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channel@8 {
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gw,mode = <1>;
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reg = <0x08>;
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label = "vdd_bat";
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};
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channel@82 {
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gw,mode = <2>;
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reg = <0x82>;
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label = "vin_aux1";
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gw,voltage-divider-ohms = <22100 1000>;
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};
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channel@84 {
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gw,mode = <2>;
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reg = <0x84>;
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label = "vin_aux2";
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gw,voltage-divider-ohms = <22100 1000>;
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};
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channel@86 {
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gw,mode = <2>;
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reg = <0x86>;
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label = "vdd_vin";
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gw,voltage-divider-ohms = <22100 1000>;
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};
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channel@88 {
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gw,mode = <2>;
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reg = <0x88>;
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label = "vdd_3p3";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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channel@8c {
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gw,mode = <2>;
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reg = <0x8c>;
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label = "vdd_2p5";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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channel@8e {
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gw,mode = <2>;
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reg = <0x8e>;
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label = "vdd_0p95";
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};
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channel@90 {
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gw,mode = <2>;
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reg = <0x90>;
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label = "vdd_soc";
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};
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channel@92 {
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gw,mode = <2>;
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reg = <0x92>;
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label = "vdd_arm";
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};
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channel@98 {
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gw,mode = <2>;
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reg = <0x98>;
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label = "vdd_1p8";
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};
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channel@9a {
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gw,mode = <2>;
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reg = <0x9a>;
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label = "vdd_1p2";
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};
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channel@9c {
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gw,mode = <2>;
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reg = <0x9c>;
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label = "vdd_dram";
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};
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channel@a2 {
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gw,mode = <2>;
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reg = <0xa2>;
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label = "vdd_gsc";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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};
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};
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gpio: gpio@23 {
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compatible = "nxp,pca9555";
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reg = <0x23>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gsc>;
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interrupts = <4>;
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};
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eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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eeprom@52 {
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compatible = "atmel,24c02";
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reg = <0x52>;
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pagesize = <16>;
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};
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eeprom@53 {
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compatible = "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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};
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rtc@68 {
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compatible = "dallas,ds1672";
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reg = <0x68>;
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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pmic@4b {
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compatible = "rohm,bd71847";
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reg = <0x4b>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio3>;
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interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
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rohm,reset-snvs-powered;
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#clock-cells = <0>;
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clocks = <&osc_32k 0>;
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clock-output-names = "clk-32k-out";
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regulators {
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/* vdd_soc: 0.805-0.900V (typ=0.8V) */
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BUCK1 {
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regulator-name = "buck1";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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};
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/* vdd_arm: 0.805-1.0V (typ=0.9V) */
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BUCK2 {
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regulator-name = "buck2";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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rohm,dvs-run-voltage = <1000000>;
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rohm,dvs-idle-voltage = <900000>;
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};
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/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
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BUCK3 {
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regulator-name = "buck3";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* vdd_3p3 */
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BUCK4 {
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regulator-name = "buck4";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* vdd_1p8 */
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BUCK5 {
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regulator-name = "buck5";
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regulator-min-microvolt = <1605000>;
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regulator-max-microvolt = <1995000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* vdd_dram */
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|
BUCK6 {
|
|
regulator-name = "buck6";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1400000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* nvcc_snvs_1p8 */
|
|
LDO1 {
|
|
regulator-name = "ldo1";
|
|
regulator-min-microvolt = <1600000>;
|
|
regulator-max-microvolt = <1900000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* vdd_snvs_0p8 */
|
|
LDO2 {
|
|
regulator-name = "ldo2";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <900000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
/* vdda_1p8 */
|
|
LDO3 {
|
|
regulator-name = "ldo3";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
LDO4 {
|
|
regulator-name = "ldo4";
|
|
regulator-min-microvolt = <900000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
LDO6 {
|
|
regulator-name = "ldo6";
|
|
regulator-min-microvolt = <900000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c3 {
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default", "gpio";
|
|
pinctrl-0 = <&pinctrl_i2c3>;
|
|
pinctrl-1 = <&pinctrl_i2c3_gpio>;
|
|
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
status = "okay";
|
|
|
|
leds_gpio: gpio@20 {
|
|
compatible = "nxp,pca9555";
|
|
reg = <0x20>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
switch: switch@5f {
|
|
compatible = "microchip,ksz9897";
|
|
reg = <0x5f>;
|
|
pinctrl-0 = <&pinctrl_ksz>;
|
|
interrupt-parent = <&gpio4>;
|
|
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
|
phy-mode = "rgmii-id";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
lan1: port@0 {
|
|
reg = <0>;
|
|
label = "lan1";
|
|
phy-mode = "internal";
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
};
|
|
|
|
lan2: port@1 {
|
|
reg = <1>;
|
|
label = "lan2";
|
|
phy-mode = "internal";
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
};
|
|
|
|
lan3: port@2 {
|
|
reg = <2>;
|
|
label = "lan3";
|
|
phy-mode = "internal";
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
};
|
|
|
|
lan4: port@3 {
|
|
reg = <3>;
|
|
label = "lan4";
|
|
phy-mode = "internal";
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
label = "cpu";
|
|
ethernet = <&fec1>;
|
|
phy-mode = "rgmii-id";
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
crypto@60 {
|
|
compatible = "atmel,atecc508a";
|
|
reg = <0x60>;
|
|
};
|
|
};
|
|
|
|
&i2c4 {
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default", "gpio";
|
|
pinctrl-0 = <&pinctrl_i2c4>;
|
|
pinctrl-1 = <&pinctrl_i2c4_gpio>;
|
|
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie_phy {
|
|
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
|
fsl,clkreq-unsupported;
|
|
clocks = <&pcie0_refclk>;
|
|
clock-names = "ref";
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pcie0>;
|
|
reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
|
|
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
|
|
<&clk IMX8MM_CLK_PCIE1_AUX>;
|
|
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
|
|
<&clk IMX8MM_CLK_PCIE1_CTRL>;
|
|
assigned-clock-rates = <10000000>, <250000000>;
|
|
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
|
|
<&clk IMX8MM_SYS_PLL2_250M>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pgc_gpu {
|
|
status = "disabled";
|
|
};
|
|
|
|
&pgc_gpumix {
|
|
status = "disabled";
|
|
};
|
|
|
|
&pgc_mipi {
|
|
status = "disabled";
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
|
|
rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
|
|
cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
|
|
dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
|
|
dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
|
|
dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
|
|
/* console */
|
|
&uart2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
|
|
cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
|
|
rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart4 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
|
|
cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
|
|
rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg1 {
|
|
dr_mode = "host";
|
|
disable-over-current;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg2 {
|
|
dr_mode = "host";
|
|
vbus-supply = <®_usb2_vbus>;
|
|
over-current-active-low;
|
|
status = "okay";
|
|
};
|
|
|
|
/* SDIO WiFi */
|
|
&usdhc1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usdhc1>;
|
|
bus-width = <4>;
|
|
non-removable;
|
|
vmmc-supply = <®_wifi>;
|
|
status = "okay";
|
|
};
|
|
|
|
/* microSD */
|
|
&usdhc2 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
|
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
|
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
|
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
|
bus-width = <4>;
|
|
vmmc-supply = <®_3p3v>;
|
|
status = "okay";
|
|
};
|
|
|
|
/* eMMC */
|
|
&usdhc3 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
&wdog1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
fsl,ext-reset-output;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_hog>;
|
|
|
|
pinctrl_hog: hoggrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
|
|
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
|
|
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
|
|
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */
|
|
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */
|
|
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */
|
|
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */
|
|
>;
|
|
};
|
|
|
|
pinctrl_fec1: fec1grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
|
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
|
|
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
|
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
|
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
|
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
|
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
|
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
|
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
|
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
|
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
|
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
|
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
|
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
|
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */
|
|
MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */
|
|
>;
|
|
};
|
|
|
|
pinctrl_gsc: gscgrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
|
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1_gpio: i2c1gpiogrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
|
|
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
|
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2_gpio: i2c2gpiogrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
|
|
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
|
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3_gpio: i2c3gpiogrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
|
|
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c4: i2c4grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
|
|
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c4_gpio: i2c4gpiogrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
|
|
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_ksz: kszgrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41
|
|
MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */
|
|
>;
|
|
};
|
|
|
|
pinctrl_pcie0: pciegrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */
|
|
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41
|
|
>;
|
|
};
|
|
|
|
pinctrl_pmic: pmicgrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
|
|
>;
|
|
};
|
|
|
|
pinctrl_reg_isouart: regisouartgrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041
|
|
>;
|
|
};
|
|
|
|
pinctrl_reg_ioexp: regioexpgrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041
|
|
>;
|
|
};
|
|
|
|
pinctrl_reg_wl: regwlgrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041
|
|
>;
|
|
};
|
|
|
|
pinctrl_reg_usb2: regusb1grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41
|
|
MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140
|
|
MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_spi1: spi1grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
|
|
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
|
|
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
|
|
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
|
|
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
|
|
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
|
|
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140
|
|
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140
|
|
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140
|
|
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1_gpio: uart1gpiogrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */
|
|
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */
|
|
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
|
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
|
|
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
|
|
MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140
|
|
MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3_gpio: uart3gpiogrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */
|
|
MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */
|
|
MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart4: uart4grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
|
|
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
|
|
MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140
|
|
MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart4_gpio: uart4gpiogrp {
|
|
fsl,pins = <
|
|
|
|
MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */
|
|
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */
|
|
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
|
|
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
|
|
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
|
|
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
|
|
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
|
|
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
|
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
|
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
|
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
|
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
|
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
|
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
|
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
|
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
|
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
|
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
|
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
|
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
|
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
|
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
|
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
|
|
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
|
|
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
|
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
|
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
|
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
|
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
|
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
|
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
|
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
|
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
|
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
|
|
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
|
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
|
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
|
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
|
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
|
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
|
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
|
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
|
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
|
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
|
|
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
|
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
|
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
|
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
|
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
|
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
|
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
|
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
|
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
|
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
|
>;
|
|
};
|
|
};
|