163 lines
2.0 KiB
Plaintext
163 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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//
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// Device Tree Source for UniPhier PXs3 Reference Board
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//
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// Copyright (C) 2017 Socionext Inc.
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// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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/dts-v1/;
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#include "uniphier-pxs3.dtsi"
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#include "uniphier-support-card.dtsi"
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/ {
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model = "UniPhier PXs3 Reference Board";
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compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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serial0 = &serial0;
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serial1 = &serialsc;
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serial2 = &serial2;
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serial3 = &serial3;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c6 = &i2c6;
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spi0 = &spi0;
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spi1 = &spi1;
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ethernet0 = ð0;
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ethernet1 = ð1;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0 0xa0000000>;
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};
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};
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ðsc {
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interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
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};
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&serialsc {
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interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
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};
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&spi0 {
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status = "okay";
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};
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&spi1 {
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status = "okay";
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};
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&serial0 {
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status = "okay";
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};
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&serial2 {
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status = "okay";
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};
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&serial3 {
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status = "okay";
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};
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&gpio {
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xirq4-hog {
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gpio-hog;
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gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
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input;
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};
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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};
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&i2c3 {
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status = "okay";
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};
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&sd {
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status = "okay";
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};
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ð0 {
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status = "okay";
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phy-handle = <ðphy0>;
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};
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&mdio0 {
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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ð1 {
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status = "okay";
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phy-handle = <ðphy1>;
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};
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&mdio1 {
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ethphy1: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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&pcie {
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status = "okay";
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};
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&nand {
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status = "okay";
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nand@0 {
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reg = <0>;
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};
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};
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&ahci0 {
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status = "okay";
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};
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&ahci1 {
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status = "okay";
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};
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&pinctrl_ether_rgmii {
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tx {
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pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1",
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"RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL";
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drive-strength = <9>;
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};
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};
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&pinctrl_ether1_rgmii {
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tx {
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pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1",
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"RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL";
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drive-strength = <9>;
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};
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};
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