478 lines
14 KiB
C
478 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Record and handle CPU attributes.
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*
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* Copyright (C) 2014 ARM Ltd.
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*/
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#include <asm/arch_timer.h>
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#include <asm/cache.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/cpufeature.h>
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#include <asm/fpsimd.h>
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/compat.h>
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#include <linux/elf.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/personality.h>
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#include <linux/preempt.h>
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#include <linux/printk.h>
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#include <linux/seq_file.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/delay.h>
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/*
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* In case the boot CPU is hotpluggable, we record its initial state and
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* current state separately. Certain system registers may contain different
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* values depending on configuration at or after reset.
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*/
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DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
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static struct cpuinfo_arm64 boot_cpu_data;
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static inline const char *icache_policy_str(int l1ip)
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{
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switch (l1ip) {
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case CTR_EL0_L1Ip_VPIPT:
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return "VPIPT";
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case CTR_EL0_L1Ip_VIPT:
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return "VIPT";
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case CTR_EL0_L1Ip_PIPT:
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return "PIPT";
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default:
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return "RESERVED/UNKNOWN";
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}
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}
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unsigned long __icache_flags;
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static const char *const hwcap_str[] = {
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[KERNEL_HWCAP_FP] = "fp",
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[KERNEL_HWCAP_ASIMD] = "asimd",
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[KERNEL_HWCAP_EVTSTRM] = "evtstrm",
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[KERNEL_HWCAP_AES] = "aes",
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[KERNEL_HWCAP_PMULL] = "pmull",
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[KERNEL_HWCAP_SHA1] = "sha1",
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[KERNEL_HWCAP_SHA2] = "sha2",
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[KERNEL_HWCAP_CRC32] = "crc32",
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[KERNEL_HWCAP_ATOMICS] = "atomics",
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[KERNEL_HWCAP_FPHP] = "fphp",
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[KERNEL_HWCAP_ASIMDHP] = "asimdhp",
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[KERNEL_HWCAP_CPUID] = "cpuid",
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[KERNEL_HWCAP_ASIMDRDM] = "asimdrdm",
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[KERNEL_HWCAP_JSCVT] = "jscvt",
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[KERNEL_HWCAP_FCMA] = "fcma",
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[KERNEL_HWCAP_LRCPC] = "lrcpc",
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[KERNEL_HWCAP_DCPOP] = "dcpop",
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[KERNEL_HWCAP_SHA3] = "sha3",
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[KERNEL_HWCAP_SM3] = "sm3",
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[KERNEL_HWCAP_SM4] = "sm4",
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[KERNEL_HWCAP_ASIMDDP] = "asimddp",
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[KERNEL_HWCAP_SHA512] = "sha512",
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[KERNEL_HWCAP_SVE] = "sve",
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[KERNEL_HWCAP_ASIMDFHM] = "asimdfhm",
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[KERNEL_HWCAP_DIT] = "dit",
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[KERNEL_HWCAP_USCAT] = "uscat",
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[KERNEL_HWCAP_ILRCPC] = "ilrcpc",
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[KERNEL_HWCAP_FLAGM] = "flagm",
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[KERNEL_HWCAP_SSBS] = "ssbs",
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[KERNEL_HWCAP_SB] = "sb",
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[KERNEL_HWCAP_PACA] = "paca",
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[KERNEL_HWCAP_PACG] = "pacg",
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[KERNEL_HWCAP_DCPODP] = "dcpodp",
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[KERNEL_HWCAP_SVE2] = "sve2",
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[KERNEL_HWCAP_SVEAES] = "sveaes",
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[KERNEL_HWCAP_SVEPMULL] = "svepmull",
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[KERNEL_HWCAP_SVEBITPERM] = "svebitperm",
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[KERNEL_HWCAP_SVESHA3] = "svesha3",
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[KERNEL_HWCAP_SVESM4] = "svesm4",
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[KERNEL_HWCAP_FLAGM2] = "flagm2",
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[KERNEL_HWCAP_FRINT] = "frint",
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[KERNEL_HWCAP_SVEI8MM] = "svei8mm",
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[KERNEL_HWCAP_SVEF32MM] = "svef32mm",
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[KERNEL_HWCAP_SVEF64MM] = "svef64mm",
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[KERNEL_HWCAP_SVEBF16] = "svebf16",
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[KERNEL_HWCAP_I8MM] = "i8mm",
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[KERNEL_HWCAP_BF16] = "bf16",
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[KERNEL_HWCAP_DGH] = "dgh",
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[KERNEL_HWCAP_RNG] = "rng",
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[KERNEL_HWCAP_BTI] = "bti",
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[KERNEL_HWCAP_MTE] = "mte",
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[KERNEL_HWCAP_ECV] = "ecv",
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[KERNEL_HWCAP_AFP] = "afp",
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[KERNEL_HWCAP_RPRES] = "rpres",
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[KERNEL_HWCAP_MTE3] = "mte3",
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[KERNEL_HWCAP_SME] = "sme",
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[KERNEL_HWCAP_SME_I16I64] = "smei16i64",
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[KERNEL_HWCAP_SME_F64F64] = "smef64f64",
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[KERNEL_HWCAP_SME_I8I32] = "smei8i32",
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[KERNEL_HWCAP_SME_F16F32] = "smef16f32",
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[KERNEL_HWCAP_SME_B16F32] = "smeb16f32",
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[KERNEL_HWCAP_SME_F32F32] = "smef32f32",
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[KERNEL_HWCAP_SME_FA64] = "smefa64",
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[KERNEL_HWCAP_WFXT] = "wfxt",
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[KERNEL_HWCAP_EBF16] = "ebf16",
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[KERNEL_HWCAP_SVE_EBF16] = "sveebf16",
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[KERNEL_HWCAP_CSSC] = "cssc",
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[KERNEL_HWCAP_RPRFM] = "rprfm",
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[KERNEL_HWCAP_SVE2P1] = "sve2p1",
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[KERNEL_HWCAP_SME2] = "sme2",
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[KERNEL_HWCAP_SME2P1] = "sme2p1",
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[KERNEL_HWCAP_SME_I16I32] = "smei16i32",
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[KERNEL_HWCAP_SME_BI32I32] = "smebi32i32",
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[KERNEL_HWCAP_SME_B16B16] = "smeb16b16",
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[KERNEL_HWCAP_SME_F16F16] = "smef16f16",
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};
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#ifdef CONFIG_COMPAT
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#define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x)
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static const char *const compat_hwcap_str[] = {
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[COMPAT_KERNEL_HWCAP(SWP)] = "swp",
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[COMPAT_KERNEL_HWCAP(HALF)] = "half",
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[COMPAT_KERNEL_HWCAP(THUMB)] = "thumb",
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[COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */
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[COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
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[COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */
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[COMPAT_KERNEL_HWCAP(VFP)] = "vfp",
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[COMPAT_KERNEL_HWCAP(EDSP)] = "edsp",
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[COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */
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[COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */
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[COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */
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[COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */
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[COMPAT_KERNEL_HWCAP(NEON)] = "neon",
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[COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3",
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[COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */
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[COMPAT_KERNEL_HWCAP(TLS)] = "tls",
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[COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4",
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[COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva",
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[COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt",
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[COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */
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[COMPAT_KERNEL_HWCAP(LPAE)] = "lpae",
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[COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm",
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[COMPAT_KERNEL_HWCAP(FPHP)] = "fphp",
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[COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp",
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[COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp",
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[COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm",
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[COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16",
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[COMPAT_KERNEL_HWCAP(I8MM)] = "i8mm",
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};
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#define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
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static const char *const compat_hwcap2_str[] = {
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[COMPAT_KERNEL_HWCAP2(AES)] = "aes",
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[COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull",
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[COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1",
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[COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2",
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[COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32",
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[COMPAT_KERNEL_HWCAP2(SB)] = "sb",
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[COMPAT_KERNEL_HWCAP2(SSBS)] = "ssbs",
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};
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#endif /* CONFIG_COMPAT */
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static int c_show(struct seq_file *m, void *v)
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{
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int i, j;
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bool compat = personality(current->personality) == PER_LINUX32;
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for_each_online_cpu(i) {
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struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
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u32 midr = cpuinfo->reg_midr;
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/*
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* glibc reads /proc/cpuinfo to determine the number of
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* online processors, looking for lines beginning with
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* "processor". Give glibc what it expects.
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*/
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seq_printf(m, "processor\t: %d\n", i);
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if (compat)
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seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
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MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
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seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
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loops_per_jiffy / (500000UL/HZ),
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loops_per_jiffy / (5000UL/HZ) % 100);
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/*
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* Dump out the common processor features in a single line.
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* Userspace should read the hwcaps with getauxval(AT_HWCAP)
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* rather than attempting to parse this, but there's a body of
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* software which does already (at least for 32-bit).
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*/
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seq_puts(m, "Features\t:");
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if (compat) {
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#ifdef CONFIG_COMPAT
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for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
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if (compat_elf_hwcap & (1 << j)) {
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/*
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* Warn once if any feature should not
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* have been present on arm64 platform.
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*/
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if (WARN_ON_ONCE(!compat_hwcap_str[j]))
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continue;
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seq_printf(m, " %s", compat_hwcap_str[j]);
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}
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}
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for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
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if (compat_elf_hwcap2 & (1 << j))
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seq_printf(m, " %s", compat_hwcap2_str[j]);
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#endif /* CONFIG_COMPAT */
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} else {
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for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
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if (cpu_have_feature(j))
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seq_printf(m, " %s", hwcap_str[j]);
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}
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seq_puts(m, "\n");
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seq_printf(m, "CPU implementer\t: 0x%02x\n",
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MIDR_IMPLEMENTOR(midr));
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seq_printf(m, "CPU architecture: 8\n");
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seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
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seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
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seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
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}
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return 0;
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}
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static void *c_start(struct seq_file *m, loff_t *pos)
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{
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return *pos < 1 ? (void *)1 : NULL;
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}
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static void *c_next(struct seq_file *m, void *v, loff_t *pos)
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{
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++*pos;
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return NULL;
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}
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static void c_stop(struct seq_file *m, void *v)
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{
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}
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const struct seq_operations cpuinfo_op = {
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.start = c_start,
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.next = c_next,
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.stop = c_stop,
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.show = c_show
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};
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static struct kobj_type cpuregs_kobj_type = {
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.sysfs_ops = &kobj_sysfs_ops,
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};
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/*
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* The ARM ARM uses the phrase "32-bit register" to describe a register
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* whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
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* no statement is made as to whether the upper 32 bits will or will not
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* be made use of in future, and between ARM DDI 0487A.c and ARM DDI
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* 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
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*
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* Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
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* registers, we expose them both as 64 bit values to cater for possible
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* future expansion without an ABI break.
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*/
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#define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
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#define CPUREGS_ATTR_RO(_name, _field) \
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static ssize_t _name##_show(struct kobject *kobj, \
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struct kobj_attribute *attr, char *buf) \
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{ \
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struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
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\
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if (info->reg_midr) \
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return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
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else \
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return 0; \
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} \
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static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
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CPUREGS_ATTR_RO(midr_el1, midr);
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CPUREGS_ATTR_RO(revidr_el1, revidr);
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CPUREGS_ATTR_RO(smidr_el1, smidr);
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static struct attribute *cpuregs_id_attrs[] = {
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&cpuregs_attr_midr_el1.attr,
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&cpuregs_attr_revidr_el1.attr,
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NULL
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};
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static const struct attribute_group cpuregs_attr_group = {
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.attrs = cpuregs_id_attrs,
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.name = "identification"
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};
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static struct attribute *sme_cpuregs_id_attrs[] = {
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&cpuregs_attr_smidr_el1.attr,
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NULL
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};
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static const struct attribute_group sme_cpuregs_attr_group = {
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.attrs = sme_cpuregs_id_attrs,
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.name = "identification"
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};
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static int cpuid_cpu_online(unsigned int cpu)
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{
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int rc;
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struct device *dev;
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struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
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dev = get_cpu_device(cpu);
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if (!dev) {
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rc = -ENODEV;
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goto out;
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}
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rc = kobject_add(&info->kobj, &dev->kobj, "regs");
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if (rc)
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goto out;
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rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
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if (rc)
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kobject_del(&info->kobj);
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if (system_supports_sme())
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rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group);
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out:
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return rc;
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}
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static int cpuid_cpu_offline(unsigned int cpu)
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{
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struct device *dev;
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struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
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dev = get_cpu_device(cpu);
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if (!dev)
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return -ENODEV;
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if (info->kobj.parent) {
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sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
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kobject_del(&info->kobj);
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}
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return 0;
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}
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static int __init cpuinfo_regs_init(void)
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{
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int cpu, ret;
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for_each_possible_cpu(cpu) {
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struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
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kobject_init(&info->kobj, &cpuregs_kobj_type);
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}
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ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
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cpuid_cpu_online, cpuid_cpu_offline);
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if (ret < 0) {
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pr_err("cpuinfo: failed to register hotplug callbacks.\n");
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return ret;
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}
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return 0;
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}
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device_initcall(cpuinfo_regs_init);
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static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
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{
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unsigned int cpu = smp_processor_id();
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u32 l1ip = CTR_L1IP(info->reg_ctr);
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switch (l1ip) {
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case CTR_EL0_L1Ip_PIPT:
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break;
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case CTR_EL0_L1Ip_VPIPT:
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set_bit(ICACHEF_VPIPT, &__icache_flags);
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break;
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case CTR_EL0_L1Ip_VIPT:
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default:
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/* Assume aliasing */
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set_bit(ICACHEF_ALIASING, &__icache_flags);
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break;
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}
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pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu);
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}
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static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
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{
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info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
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info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
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info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
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info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
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info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
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info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
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info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
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info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
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info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
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info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
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info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
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info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
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info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
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info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
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info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
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info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
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info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
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info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
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|
info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
|
|
info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
|
|
info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
|
|
}
|
|
|
|
static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
|
|
{
|
|
info->reg_cntfrq = arch_timer_get_cntfrq();
|
|
/*
|
|
* Use the effective value of the CTR_EL0 than the raw value
|
|
* exposed by the CPU. CTR_EL0.IDC field value must be interpreted
|
|
* with the CLIDR_EL1 fields to avoid triggering false warnings
|
|
* when there is a mismatch across the CPUs. Keep track of the
|
|
* effective value of the CTR_EL0 in our internal records for
|
|
* accurate sanity check and feature enablement.
|
|
*/
|
|
info->reg_ctr = read_cpuid_effective_cachetype();
|
|
info->reg_dczid = read_cpuid(DCZID_EL0);
|
|
info->reg_midr = read_cpuid_id();
|
|
info->reg_revidr = read_cpuid(REVIDR_EL1);
|
|
|
|
info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
|
|
info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
|
|
info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
|
|
info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
|
|
info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
|
|
info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
|
|
info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
|
|
info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
|
|
info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
|
|
info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
|
|
info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
|
|
info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1);
|
|
|
|
if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
|
|
info->reg_gmid = read_cpuid(GMID_EL1);
|
|
|
|
if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
|
|
__cpuinfo_store_cpu_32bit(&info->aarch32);
|
|
|
|
cpuinfo_detect_icache_policy(info);
|
|
}
|
|
|
|
void cpuinfo_store_cpu(void)
|
|
{
|
|
struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
|
|
__cpuinfo_store_cpu(info);
|
|
update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
|
|
}
|
|
|
|
void __init cpuinfo_store_boot_cpu(void)
|
|
{
|
|
struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
|
|
__cpuinfo_store_cpu(info);
|
|
|
|
boot_cpu_data = *info;
|
|
init_cpu_features(&boot_cpu_data);
|
|
}
|