327 lines
7.9 KiB
C
327 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* the ISA Virtual Support Module of AMD CS5536
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*
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* Copyright (C) 2007 Lemote, Inc.
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* Author : jlliu, liujl@lemote.com
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*
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* Copyright (C) 2009 Lemote, Inc.
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* Author: Wu Zhangjin, wuzhangjin@gmail.com
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*/
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#include <linux/pci.h>
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#include <cs5536/cs5536.h>
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#include <cs5536/cs5536_pci.h>
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/* common variables for PCI_ISA_READ/WRITE_BAR */
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static const u32 divil_msr_reg[6] = {
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DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO),
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DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ),
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DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI),
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};
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static const u32 soft_bar_flag[6] = {
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SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG,
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SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG,
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};
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static const u32 sb_msr_reg[6] = {
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SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2),
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SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5),
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};
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static const u32 bar_space_range[6] = {
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CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE,
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CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE,
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};
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static const int bar_space_len[6] = {
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CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH,
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CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH,
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};
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/*
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* enable the divil module bar space.
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*
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* For all the DIVIL module LBAR, you should control the DIVIL LBAR reg
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* and the RCONFx(0~5) reg to use the modules.
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*/
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static void divil_lbar_enable(void)
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{
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u32 hi, lo;
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int offset;
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/*
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* The DIVIL IRQ is not used yet. and make the RCONF0 reserved.
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*/
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for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
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_rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
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hi |= 0x01;
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_wrmsr(DIVIL_MSR_REG(offset), hi, lo);
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}
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}
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/*
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* disable the divil module bar space.
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*/
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static void divil_lbar_disable(void)
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{
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u32 hi, lo;
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int offset;
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for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
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_rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
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hi &= ~0x01;
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_wrmsr(DIVIL_MSR_REG(offset), hi, lo);
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}
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}
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/*
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* BAR write: write value to the n BAR
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*/
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void pci_isa_write_bar(int n, u32 value)
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{
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u32 hi = 0, lo = value;
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if (value == PCI_BAR_RANGE_MASK) {
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_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
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lo |= soft_bar_flag[n];
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_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
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} else if (value & 0x01) {
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/* NATIVE reg */
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hi = 0x0000f001;
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lo &= bar_space_range[n];
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_wrmsr(divil_msr_reg[n], hi, lo);
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/* RCONFx is 4bytes in units for I/O space */
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hi = ((value & 0x000ffffc) << 12) |
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((bar_space_len[n] - 4) << 12) | 0x01;
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lo = ((value & 0x000ffffc) << 12) | 0x01;
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_wrmsr(sb_msr_reg[n], hi, lo);
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}
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}
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/*
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* BAR read: read the n BAR
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*/
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u32 pci_isa_read_bar(int n)
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{
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u32 conf_data = 0;
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u32 hi, lo;
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_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
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if (lo & soft_bar_flag[n]) {
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conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO;
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lo &= ~soft_bar_flag[n];
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_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
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} else {
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_rdmsr(divil_msr_reg[n], &hi, &lo);
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conf_data = lo & bar_space_range[n];
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conf_data |= 0x01;
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conf_data &= ~0x02;
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}
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return conf_data;
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}
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/*
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* isa_write: ISA write transfer
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*
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* We assume that this is not a bus master transfer.
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*/
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void pci_isa_write_reg(int reg, u32 value)
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{
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u32 hi = 0, lo = value;
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u32 temp;
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switch (reg) {
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case PCI_COMMAND:
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if (value & PCI_COMMAND_IO)
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divil_lbar_enable();
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else
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divil_lbar_disable();
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break;
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case PCI_STATUS:
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_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
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temp = lo & 0x0000ffff;
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if ((value & PCI_STATUS_SIG_TARGET_ABORT) &&
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(lo & SB_TAS_ERR_EN))
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temp |= SB_TAS_ERR_FLAG;
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if ((value & PCI_STATUS_REC_TARGET_ABORT) &&
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(lo & SB_TAR_ERR_EN))
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temp |= SB_TAR_ERR_FLAG;
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if ((value & PCI_STATUS_REC_MASTER_ABORT)
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&& (lo & SB_MAR_ERR_EN))
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temp |= SB_MAR_ERR_FLAG;
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if ((value & PCI_STATUS_DETECTED_PARITY)
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&& (lo & SB_PARE_ERR_EN))
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temp |= SB_PARE_ERR_FLAG;
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lo = temp;
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_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
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break;
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case PCI_CACHE_LINE_SIZE:
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value &= 0x0000ff00;
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_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
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hi &= 0xffffff00;
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hi |= (value >> 8);
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_wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
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break;
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case PCI_BAR0_REG:
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pci_isa_write_bar(0, value);
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break;
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case PCI_BAR1_REG:
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pci_isa_write_bar(1, value);
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break;
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case PCI_BAR2_REG:
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pci_isa_write_bar(2, value);
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break;
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case PCI_BAR3_REG:
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pci_isa_write_bar(3, value);
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break;
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case PCI_BAR4_REG:
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pci_isa_write_bar(4, value);
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break;
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case PCI_BAR5_REG:
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pci_isa_write_bar(5, value);
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break;
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case PCI_UART1_INT_REG:
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_rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
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/* disable uart1 interrupt in PIC */
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lo &= ~(0xf << 24);
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if (value) /* enable uart1 interrupt in PIC */
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lo |= (CS5536_UART1_INTR << 24);
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_wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
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break;
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case PCI_UART2_INT_REG:
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_rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
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/* disable uart2 interrupt in PIC */
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lo &= ~(0xf << 28);
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if (value) /* enable uart2 interrupt in PIC */
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lo |= (CS5536_UART2_INTR << 28);
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_wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
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break;
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case PCI_ISA_FIXUP_REG:
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if (value) {
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/* enable the TARGET ABORT/MASTER ABORT etc. */
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_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
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lo |= 0x00000063;
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_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
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}
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default:
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/* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */
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break;
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}
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}
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/*
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* isa_read: ISA read transfers
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*
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* We assume that this is not a bus master transfer.
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*/
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u32 pci_isa_read_reg(int reg)
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{
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u32 conf_data = 0;
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u32 hi, lo;
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switch (reg) {
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case PCI_VENDOR_ID:
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conf_data =
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CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID);
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break;
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case PCI_COMMAND:
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/* we just check the first LBAR for the IO enable bit, */
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/* maybe we should changed later. */
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_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);
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if (hi & 0x01)
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conf_data |= PCI_COMMAND_IO;
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break;
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case PCI_STATUS:
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conf_data |= PCI_STATUS_66MHZ;
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conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
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conf_data |= PCI_STATUS_FAST_BACK;
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_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
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if (lo & SB_TAS_ERR_FLAG)
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conf_data |= PCI_STATUS_SIG_TARGET_ABORT;
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if (lo & SB_TAR_ERR_FLAG)
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conf_data |= PCI_STATUS_REC_TARGET_ABORT;
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if (lo & SB_MAR_ERR_FLAG)
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conf_data |= PCI_STATUS_REC_MASTER_ABORT;
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if (lo & SB_PARE_ERR_FLAG)
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conf_data |= PCI_STATUS_DETECTED_PARITY;
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break;
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case PCI_CLASS_REVISION:
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_rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo);
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conf_data = lo & 0x000000ff;
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conf_data |= (CS5536_ISA_CLASS_CODE << 8);
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break;
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case PCI_CACHE_LINE_SIZE:
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_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
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hi &= 0x000000f8;
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conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi);
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break;
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/*
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* we only use the LBAR of DIVIL, no RCONF used.
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* all of them are IO space.
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*/
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case PCI_BAR0_REG:
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return pci_isa_read_bar(0);
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break;
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case PCI_BAR1_REG:
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return pci_isa_read_bar(1);
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break;
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case PCI_BAR2_REG:
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return pci_isa_read_bar(2);
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break;
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case PCI_BAR3_REG:
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break;
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case PCI_BAR4_REG:
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return pci_isa_read_bar(4);
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break;
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case PCI_BAR5_REG:
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return pci_isa_read_bar(5);
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break;
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case PCI_CARDBUS_CIS:
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conf_data = PCI_CARDBUS_CIS_POINTER;
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break;
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case PCI_SUBSYSTEM_VENDOR_ID:
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conf_data =
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CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID);
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break;
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case PCI_ROM_ADDRESS:
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conf_data = PCI_EXPANSION_ROM_BAR;
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break;
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case PCI_CAPABILITY_LIST:
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conf_data = PCI_CAPLIST_POINTER;
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break;
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case PCI_INTERRUPT_LINE:
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/* no interrupt used here */
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conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00);
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break;
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default:
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break;
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}
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return conf_data;
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}
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/*
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* The mfgpt timer interrupt is running early, so we must keep the south bridge
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* mmio always enabled. Otherwise we may race with the PCI configuration which
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* may temporarily disable it. When that happens and the timer interrupt fires,
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* we are not able to clear it and the system will hang.
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*/
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static void cs5536_isa_mmio_always_on(struct pci_dev *dev)
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{
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dev->mmio_always_on = 1;
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}
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
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PCI_CLASS_BRIDGE_ISA, 8, cs5536_isa_mmio_always_on);
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