522 lines
15 KiB
C
522 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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*/
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/*
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* Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
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* and interrupt. PCI interface supports MMIO access method, but does not
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* seem to support I/O ports.
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*
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* Read/write operation in the region 0x80000000-0xBFFFFFFF causes
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* a memory read/write command on the PCI bus. 30 LSBs of address on
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* the bus are taken from memory read/write request and 2 MSBs are
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* determined by PCI unit configuration.
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*
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* To work with the configuration space instead of memory is necessary set
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* the CFG_SEL bit in the PCI_MISC_CONFIG register.
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*
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* Devices on the bus can perform DMA requests via chip BAR1. PCI host
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* controller BARs are programmend as if an external device is programmed.
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* Which means that during configuration, IDSEL pin of the chip should be
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* asserted.
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*
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* We know (and support) only one board that uses the PCI interface -
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* Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
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* AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
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* and IDSEL pin of AR2315 is connected to AD[16] line.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/dma-direct.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <asm/paccess.h>
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/*
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* PCI Bus Interface Registers
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*/
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#define AR2315_PCI_1MS_REG 0x0008
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#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
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#define AR2315_PCI_MISC_CONFIG 0x000c
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#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
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#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */
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#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
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#define AR2315_PCIMISC_RST_MODE 0x00000030
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#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
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#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
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#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
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#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
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#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
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#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
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#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
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#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
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* disable */
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#define AR2315_PCI_OUT_TSTAMP 0x0010
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#define AR2315_PCI_UNCACHE_CFG 0x0014
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#define AR2315_PCI_IN_EN 0x0100
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#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
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#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
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#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
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#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
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#define AR2315_PCI_IN_DIS 0x0104
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#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
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#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
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#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
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#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
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#define AR2315_PCI_IN_PTR 0x0200
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#define AR2315_PCI_OUT_EN 0x0400
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#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
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#define AR2315_PCI_OUT_DIS 0x0404
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#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
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#define AR2315_PCI_OUT_PTR 0x0408
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/* PCI interrupt status (write one to clear) */
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#define AR2315_PCI_ISR 0x0500
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#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
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#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
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#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
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#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
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#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
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#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
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#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
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#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
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#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
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#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
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#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
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#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
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/* PCI interrupt mask */
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#define AR2315_PCI_IMR 0x0504
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/* Global PCI interrupt enable */
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#define AR2315_PCI_IER 0x0508
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#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
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#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
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#define AR2315_PCI_HOST_IN_EN 0x0800
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#define AR2315_PCI_HOST_IN_DIS 0x0804
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#define AR2315_PCI_HOST_IN_PTR 0x0810
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#define AR2315_PCI_HOST_OUT_EN 0x0900
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#define AR2315_PCI_HOST_OUT_DIS 0x0904
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#define AR2315_PCI_HOST_OUT_PTR 0x0908
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/*
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* PCI interrupts, which share IP5
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* Keep ordered according to AR2315_PCI_INT_XXX bits
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*/
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#define AR2315_PCI_IRQ_EXT 25
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#define AR2315_PCI_IRQ_ABORT 26
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#define AR2315_PCI_IRQ_COUNT 27
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/* Arbitrary size of memory region to access the configuration space */
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#define AR2315_PCI_CFG_SIZE 0x00100000
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#define AR2315_PCI_HOST_SLOT 3
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#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
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/*
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* We need some arbitrary non-zero value to be programmed to the BAR1 register
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* of PCI host controller to enable DMA. The same value should be used as the
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* offset to calculate the physical address of DMA buffer for PCI devices.
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*/
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#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
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/* ??? access BAR */
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#define AR2315_PCI_HOST_MBAR0 0x10000000
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/* RAM access BAR */
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#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
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/* ??? access BAR */
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#define AR2315_PCI_HOST_MBAR2 0x30000000
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struct ar2315_pci_ctrl {
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void __iomem *cfg_mem;
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void __iomem *mmr_mem;
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unsigned irq;
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unsigned irq_ext;
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struct irq_domain *domain;
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struct pci_controller pci_ctrl;
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struct resource mem_res;
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struct resource io_res;
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};
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static inline dma_addr_t ar2315_dev_offset(struct device *dev)
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{
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if (dev && dev_is_pci(dev))
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return AR2315_PCI_HOST_SDRAM_BASEADDR;
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return 0;
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}
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dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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return paddr + ar2315_dev_offset(dev);
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}
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phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
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{
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return dma_addr - ar2315_dev_offset(dev);
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}
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static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
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{
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struct pci_controller *hose = bus->sysdata;
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return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
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}
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static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
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{
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return __raw_readl(apc->mmr_mem + reg);
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}
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static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
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u32 val)
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{
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__raw_writel(val, apc->mmr_mem + reg);
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}
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static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
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u32 mask, u32 val)
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{
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u32 ret = ar2315_pci_reg_read(apc, reg);
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ret &= ~mask;
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ret |= val;
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ar2315_pci_reg_write(apc, reg, ret);
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}
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static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
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int where, int size, u32 *ptr, bool write)
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{
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int func = PCI_FUNC(devfn);
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int dev = PCI_SLOT(devfn);
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u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
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u32 mask = 0xffffffff >> 8 * (4 - size);
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u32 sh = (where & 3) * 8;
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u32 value, isr;
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/* Prevent access past the remapped area */
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if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Clear pending errors */
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ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
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/* Select Configuration access */
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ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
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AR2315_PCIMISC_CFG_SEL);
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mb(); /* PCI must see space change before we begin */
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value = __raw_readl(apc->cfg_mem + addr);
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isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
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if (isr & AR2315_PCI_INT_ABORT)
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goto exit_err;
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if (write) {
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value = (value & ~(mask << sh)) | *ptr << sh;
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__raw_writel(value, apc->cfg_mem + addr);
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isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
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if (isr & AR2315_PCI_INT_ABORT)
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goto exit_err;
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} else {
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*ptr = (value >> sh) & mask;
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}
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goto exit;
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exit_err:
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ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
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if (!write)
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*ptr = 0xffffffff;
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exit:
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/* Select Memory access */
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ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
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0);
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return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
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PCIBIOS_SUCCESSFUL;
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}
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static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
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unsigned devfn, int where, u32 *val)
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{
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return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
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false);
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}
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static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
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unsigned devfn, int where, u32 val)
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{
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return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
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true);
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}
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static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
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int size, u32 *value)
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{
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struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
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if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
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}
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static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
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int size, u32 value)
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{
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struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
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if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
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}
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static struct pci_ops ar2315_pci_ops = {
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.read = ar2315_pci_cfg_read,
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.write = ar2315_pci_cfg_write,
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};
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static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
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{
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unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
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int res;
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u32 id;
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res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
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if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
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return -ENODEV;
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/* Program MBARs */
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ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
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AR2315_PCI_HOST_MBAR0);
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ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
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AR2315_PCI_HOST_MBAR1);
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ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
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AR2315_PCI_HOST_MBAR2);
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/* Run */
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ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
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PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
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PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
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return 0;
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}
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static void ar2315_pci_irq_handler(struct irq_desc *desc)
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{
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struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
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u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
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ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
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int ret = 0;
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if (pending)
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ret = generic_handle_domain_irq(apc->domain, __ffs(pending));
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if (!pending || ret)
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spurious_interrupt();
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}
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static void ar2315_pci_irq_mask(struct irq_data *d)
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{
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struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
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ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
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}
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static void ar2315_pci_irq_mask_ack(struct irq_data *d)
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{
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struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
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u32 m = BIT(d->hwirq);
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ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
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ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
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}
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static void ar2315_pci_irq_unmask(struct irq_data *d)
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{
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struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
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ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
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}
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static struct irq_chip ar2315_pci_irq_chip = {
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.name = "AR2315-PCI",
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.irq_mask = ar2315_pci_irq_mask,
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.irq_mask_ack = ar2315_pci_irq_mask_ack,
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.irq_unmask = ar2315_pci_irq_unmask,
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};
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static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, d->host_data);
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return 0;
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}
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static const struct irq_domain_ops ar2315_pci_irq_domain_ops = {
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.map = ar2315_pci_irq_map,
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};
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static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
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{
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ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
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ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
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AR2315_PCI_INT_EXT), 0);
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apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
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irq_set_chained_handler_and_data(apc->irq, ar2315_pci_irq_handler,
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apc);
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/* Clear any pending Abort or external Interrupts
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* and enable interrupt processing */
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ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
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AR2315_PCI_INT_EXT);
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ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
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}
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static int ar2315_pci_probe(struct platform_device *pdev)
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{
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struct ar2315_pci_ctrl *apc;
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struct device *dev = &pdev->dev;
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struct resource *res;
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int irq, err;
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apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
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if (!apc)
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return -ENOMEM;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return -EINVAL;
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apc->irq = irq;
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apc->mmr_mem = devm_platform_ioremap_resource_byname(pdev,
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"ar2315-pci-ctrl");
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if (IS_ERR(apc->mmr_mem))
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return PTR_ERR(apc->mmr_mem);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"ar2315-pci-ext");
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if (!res)
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return -EINVAL;
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apc->mem_res.name = "AR2315 PCI mem space";
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apc->mem_res.parent = res;
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apc->mem_res.start = res->start;
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apc->mem_res.end = res->end;
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apc->mem_res.flags = IORESOURCE_MEM;
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/* Remap PCI config space */
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apc->cfg_mem = devm_ioremap(dev, res->start,
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AR2315_PCI_CFG_SIZE);
|
|
if (!apc->cfg_mem) {
|
|
dev_err(dev, "failed to remap PCI config space\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
|
|
ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
|
|
AR2315_PCIMISC_RST_MODE,
|
|
AR2315_PCIRST_LOW);
|
|
msleep(100);
|
|
|
|
/* Bring the PCI out of reset */
|
|
ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
|
|
AR2315_PCIMISC_RST_MODE,
|
|
AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
|
|
|
|
ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
|
|
0x1E | /* 1GB uncached */
|
|
(1 << 5) | /* Enable uncached */
|
|
(0x2 << 30) /* Base: 0x80000000 */);
|
|
ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
|
|
|
|
msleep(500);
|
|
|
|
err = ar2315_pci_host_setup(apc);
|
|
if (err)
|
|
return err;
|
|
|
|
apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
|
|
&ar2315_pci_irq_domain_ops, apc);
|
|
if (!apc->domain) {
|
|
dev_err(dev, "failed to add IRQ domain\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ar2315_pci_irq_init(apc);
|
|
|
|
/* PCI controller does not support I/O ports */
|
|
apc->io_res.name = "AR2315 IO space";
|
|
apc->io_res.start = 0;
|
|
apc->io_res.end = 0;
|
|
apc->io_res.flags = IORESOURCE_IO;
|
|
|
|
apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
|
|
apc->pci_ctrl.mem_resource = &apc->mem_res;
|
|
apc->pci_ctrl.io_resource = &apc->io_res;
|
|
|
|
register_pci_controller(&apc->pci_ctrl);
|
|
|
|
dev_info(dev, "register PCI controller\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ar2315_pci_driver = {
|
|
.probe = ar2315_pci_probe,
|
|
.driver = {
|
|
.name = "ar2315-pci",
|
|
},
|
|
};
|
|
|
|
static int __init ar2315_pci_init(void)
|
|
{
|
|
return platform_driver_register(&ar2315_pci_driver);
|
|
}
|
|
arch_initcall(ar2315_pci_init);
|
|
|
|
int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
|
{
|
|
struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
|
|
|
|
return slot ? 0 : apc->irq_ext;
|
|
}
|
|
|
|
int pcibios_plat_dev_init(struct pci_dev *dev)
|
|
{
|
|
return 0;
|
|
}
|