399 lines
9.4 KiB
C
399 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2013 John Crispin <john@phrozen.org>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/bug.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7620.h>
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#include "common.h"
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/* analog */
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#define PMU0_CFG 0x88
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#define PMU_SW_SET BIT(28)
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#define A_DCDC_EN BIT(24)
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#define A_SSC_PERI BIT(19)
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#define A_SSC_GEN BIT(18)
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#define A_SSC_M 0x3
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#define A_SSC_S 16
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#define A_DLY_M 0x7
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#define A_DLY_S 8
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#define A_VTUNE_M 0xff
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/* digital */
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#define PMU1_CFG 0x8C
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#define DIG_SW_SEL BIT(25)
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/* clock scaling */
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#define CLKCFG_FDIV_MASK 0x1f00
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#define CLKCFG_FDIV_USB_VAL 0x0300
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#define CLKCFG_FFRAC_MASK 0x001f
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#define CLKCFG_FFRAC_USB_VAL 0x0003
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/* EFUSE bits */
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#define EFUSE_MT7688 0x100000
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/* DRAM type bit */
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#define DRAM_TYPE_MT7628_MASK 0x1
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/* does the board have sdram or ddram */
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static int dram_type;
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static __init u32
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mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
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{
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u64 t;
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t = ref_rate;
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t *= mul;
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do_div(t, div);
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return t;
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}
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#define MHZ(x) ((x) * 1000 * 1000)
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static __init unsigned long
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mt7620_get_xtal_rate(void)
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{
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u32 reg;
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reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
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if (reg & SYSCFG0_XTAL_FREQ_SEL)
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return MHZ(40);
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return MHZ(20);
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}
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static __init unsigned long
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mt7620_get_periph_rate(unsigned long xtal_rate)
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{
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u32 reg;
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reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
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if (reg & CLKCFG0_PERI_CLK_SEL)
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return xtal_rate;
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return MHZ(40);
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}
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static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
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static __init unsigned long
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mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
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{
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u32 reg;
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u32 mul;
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u32 div;
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reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
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if (reg & CPLL_CFG0_BYPASS_REF_CLK)
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return xtal_rate;
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if ((reg & CPLL_CFG0_SW_CFG) == 0)
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return MHZ(600);
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mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
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CPLL_CFG0_PLL_MULT_RATIO_MASK;
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mul += 24;
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if (reg & CPLL_CFG0_LC_CURFCK)
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mul *= 2;
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div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
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CPLL_CFG0_PLL_DIV_RATIO_MASK;
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WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
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return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
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}
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static __init unsigned long
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mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
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{
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u32 reg;
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reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
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if (reg & CPLL_CFG1_CPU_AUX1)
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return xtal_rate;
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if (reg & CPLL_CFG1_CPU_AUX0)
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return MHZ(480);
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return cpu_pll_rate;
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}
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static __init unsigned long
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mt7620_get_cpu_rate(unsigned long pll_rate)
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{
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u32 reg;
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u32 mul;
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u32 div;
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reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
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mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
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div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
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CPU_SYS_CLKCFG_CPU_FDIV_MASK;
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return mt7620_calc_rate(pll_rate, mul, div);
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}
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static const u32 mt7620_ocp_dividers[16] __initconst = {
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[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
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[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
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[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
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[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
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[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
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};
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static __init unsigned long
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mt7620_get_dram_rate(unsigned long pll_rate)
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{
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if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
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return pll_rate / 4;
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return pll_rate / 3;
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}
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static __init unsigned long
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mt7620_get_sys_rate(unsigned long cpu_rate)
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{
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u32 reg;
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u32 ocp_ratio;
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u32 div;
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reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
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ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
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CPU_SYS_CLKCFG_OCP_RATIO_MASK;
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if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
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return cpu_rate;
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div = mt7620_ocp_dividers[ocp_ratio];
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if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
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return cpu_rate;
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return cpu_rate / div;
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}
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void __init ralink_clk_init(void)
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{
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unsigned long xtal_rate;
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unsigned long cpu_pll_rate;
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unsigned long pll_rate;
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unsigned long cpu_rate;
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unsigned long sys_rate;
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unsigned long dram_rate;
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unsigned long periph_rate;
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unsigned long pcmi2s_rate;
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xtal_rate = mt7620_get_xtal_rate();
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#define RFMT(label) label ":%lu.%03luMHz "
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#define RINT(x) ((x) / 1000000)
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#define RFRAC(x) (((x) / 1000) % 1000)
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if (is_mt76x8()) {
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if (xtal_rate == MHZ(40))
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cpu_rate = MHZ(580);
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else
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cpu_rate = MHZ(575);
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dram_rate = sys_rate = cpu_rate / 3;
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periph_rate = MHZ(40);
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pcmi2s_rate = MHZ(480);
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ralink_clk_add("10000d00.uartlite", periph_rate);
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ralink_clk_add("10000e00.uartlite", periph_rate);
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} else {
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cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
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pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
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cpu_rate = mt7620_get_cpu_rate(pll_rate);
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dram_rate = mt7620_get_dram_rate(pll_rate);
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sys_rate = mt7620_get_sys_rate(cpu_rate);
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periph_rate = mt7620_get_periph_rate(xtal_rate);
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pcmi2s_rate = periph_rate;
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pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
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RINT(xtal_rate), RFRAC(xtal_rate),
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RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
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RINT(pll_rate), RFRAC(pll_rate));
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ralink_clk_add("10000500.uart", periph_rate);
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}
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pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
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RINT(cpu_rate), RFRAC(cpu_rate),
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RINT(dram_rate), RFRAC(dram_rate),
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RINT(sys_rate), RFRAC(sys_rate),
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RINT(periph_rate), RFRAC(periph_rate));
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#undef RFRAC
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#undef RINT
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#undef RFMT
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ralink_clk_add("cpu", cpu_rate);
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ralink_clk_add("10000100.timer", periph_rate);
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ralink_clk_add("10000120.watchdog", periph_rate);
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ralink_clk_add("10000900.i2c", periph_rate);
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ralink_clk_add("10000a00.i2s", pcmi2s_rate);
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ralink_clk_add("10000b00.spi", sys_rate);
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ralink_clk_add("10000b40.spi", sys_rate);
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ralink_clk_add("10000c00.uartlite", periph_rate);
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ralink_clk_add("10000d00.uart1", periph_rate);
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ralink_clk_add("10000e00.uart2", periph_rate);
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ralink_clk_add("10180000.wmac", xtal_rate);
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if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
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/*
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* When the CPU goes into sleep mode, the BUS clock will be
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* too low for USB to function properly. Adjust the busses
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* fractional divider to fix this
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*/
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u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
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val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
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val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
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rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
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}
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}
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void __init ralink_of_remap(void)
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{
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rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
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rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
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if (!rt_sysc_membase || !rt_memc_membase)
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panic("Failed to remap core resources");
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}
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static __init void
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mt7620_dram_init(struct ralink_soc_info *soc_info)
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{
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switch (dram_type) {
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case SYSCFG0_DRAM_TYPE_SDRAM:
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pr_info("Board has SDRAM\n");
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soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
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soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
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break;
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case SYSCFG0_DRAM_TYPE_DDR1:
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pr_info("Board has DDR1\n");
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soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
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soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
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break;
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case SYSCFG0_DRAM_TYPE_DDR2:
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pr_info("Board has DDR2\n");
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soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
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soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
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break;
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default:
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BUG();
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}
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}
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static __init void
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mt7628_dram_init(struct ralink_soc_info *soc_info)
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{
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switch (dram_type) {
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case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
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pr_info("Board has DDR1\n");
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soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
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soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
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break;
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case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
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pr_info("Board has DDR2\n");
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soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
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soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
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break;
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default:
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BUG();
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}
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}
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void __init prom_soc_init(struct ralink_soc_info *soc_info)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
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unsigned char *name = NULL;
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u32 n0;
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u32 n1;
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u32 rev;
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u32 cfg0;
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u32 pmu0;
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u32 pmu1;
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u32 bga;
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n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
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bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
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if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
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if (bga) {
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ralink_soc = MT762X_SOC_MT7620A;
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name = "MT7620A";
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soc_info->compatible = "ralink,mt7620a-soc";
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} else {
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ralink_soc = MT762X_SOC_MT7620N;
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name = "MT7620N";
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soc_info->compatible = "ralink,mt7620n-soc";
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}
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} else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
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u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
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if (efuse & EFUSE_MT7688) {
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ralink_soc = MT762X_SOC_MT7688;
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name = "MT7688";
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} else {
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ralink_soc = MT762X_SOC_MT7628AN;
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name = "MT7628AN";
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}
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soc_info->compatible = "ralink,mt7628an-soc";
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} else {
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panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
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}
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snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
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"MediaTek %s ver:%u eco:%u",
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name,
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(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
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(rev & CHIP_REV_ECO_MASK));
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cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
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if (is_mt76x8()) {
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dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
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} else {
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dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
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SYSCFG0_DRAM_TYPE_MASK;
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if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN)
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dram_type = SYSCFG0_DRAM_TYPE_SDRAM;
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}
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soc_info->mem_base = MT7620_DRAM_BASE;
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if (is_mt76x8())
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mt7628_dram_init(soc_info);
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else
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mt7620_dram_init(soc_info);
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pmu0 = __raw_readl(sysc + PMU0_CFG);
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pmu1 = __raw_readl(sysc + PMU1_CFG);
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pr_info("Analog PMU set to %s control\n",
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(pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
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pr_info("Digital PMU set to %s control\n",
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(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
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}
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