674 lines
16 KiB
C
674 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Unaligned memory access handler
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*
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* Copyright (C) 2001 Randolph Chung <tausq@debian.org>
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* Copyright (C) 2022 Helge Deller <deller@gmx.de>
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* Significantly tweaked by LaMont Jones <lamont@debian.org>
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*/
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#include <linux/sched/signal.h>
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#include <linux/signal.h>
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#include <linux/ratelimit.h>
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#include <linux/uaccess.h>
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#include <asm/hardirq.h>
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#include <asm/traps.h>
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/* #define DEBUG_UNALIGNED 1 */
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#ifdef DEBUG_UNALIGNED
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#define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define RFMT "%#08lx"
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/* 1111 1100 0000 0000 0001 0011 1100 0000 */
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#define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
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#define OPCODE2(a,b) ((a)<<26|(b)<<1)
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#define OPCODE3(a,b) ((a)<<26|(b)<<2)
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#define OPCODE4(a) ((a)<<26)
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#define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
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#define OPCODE2_MASK OPCODE2(0x3f,1)
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#define OPCODE3_MASK OPCODE3(0x3f,1)
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#define OPCODE4_MASK OPCODE4(0x3f)
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/* skip LDB - never unaligned (index) */
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#define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
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#define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
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#define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
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#define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
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#define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
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#define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
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#define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
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/* skip LDB - never unaligned (short) */
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#define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
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#define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
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#define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
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#define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
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#define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
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#define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
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#define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
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/* skip STB - never unaligned */
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#define OPCODE_STH OPCODE1(0x03,1,0x9)
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#define OPCODE_STW OPCODE1(0x03,1,0xa)
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#define OPCODE_STD OPCODE1(0x03,1,0xb)
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/* skip STBY - never unaligned */
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/* skip STDBY - never unaligned */
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#define OPCODE_STWA OPCODE1(0x03,1,0xe)
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#define OPCODE_STDA OPCODE1(0x03,1,0xf)
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#define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
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#define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
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#define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
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#define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
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#define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
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#define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
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#define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
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#define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
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#define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
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#define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
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#define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
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#define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
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#define OPCODE_LDD_L OPCODE2(0x14,0)
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#define OPCODE_FLDD_L OPCODE2(0x14,1)
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#define OPCODE_STD_L OPCODE2(0x1c,0)
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#define OPCODE_FSTD_L OPCODE2(0x1c,1)
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#define OPCODE_LDW_M OPCODE3(0x17,1)
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#define OPCODE_FLDW_L OPCODE3(0x17,0)
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#define OPCODE_FSTW_L OPCODE3(0x1f,0)
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#define OPCODE_STW_M OPCODE3(0x1f,1)
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#define OPCODE_LDH_L OPCODE4(0x11)
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#define OPCODE_LDW_L OPCODE4(0x12)
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#define OPCODE_LDWM OPCODE4(0x13)
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#define OPCODE_STH_L OPCODE4(0x19)
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#define OPCODE_STW_L OPCODE4(0x1A)
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#define OPCODE_STWM OPCODE4(0x1B)
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#define MAJOR_OP(i) (((i)>>26)&0x3f)
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#define R1(i) (((i)>>21)&0x1f)
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#define R2(i) (((i)>>16)&0x1f)
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#define R3(i) ((i)&0x1f)
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#define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
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#define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
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#define IM5_2(i) IM((i)>>16,5)
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#define IM5_3(i) IM((i),5)
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#define IM14(i) IM((i),14)
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#define ERR_NOTHANDLED -1
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int unaligned_enabled __read_mostly = 1;
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static int emulate_ldh(struct pt_regs *regs, int toreg)
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{
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unsigned long saddr = regs->ior;
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unsigned long val = 0, temp1;
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ASM_EXCEPTIONTABLE_VAR(ret);
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DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
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regs->isr, regs->ior, toreg);
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__asm__ __volatile__ (
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" mtsp %4, %%sr1\n"
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"1: ldbs 0(%%sr1,%3), %2\n"
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"2: ldbs 1(%%sr1,%3), %0\n"
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" depw %2, 23, 24, %0\n"
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"3: \n"
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
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: "+r" (val), "+r" (ret), "=&r" (temp1)
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: "r" (saddr), "r" (regs->isr) );
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DPRINTF("val = " RFMT "\n", val);
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if (toreg)
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regs->gr[toreg] = val;
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return ret;
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}
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static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
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{
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unsigned long saddr = regs->ior;
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unsigned long val = 0, temp1, temp2;
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ASM_EXCEPTIONTABLE_VAR(ret);
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DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
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regs->isr, regs->ior, toreg);
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__asm__ __volatile__ (
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" zdep %4,28,2,%2\n" /* r19=(ofs&3)*8 */
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" mtsp %5, %%sr1\n"
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" depw %%r0,31,2,%4\n"
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"1: ldw 0(%%sr1,%4),%0\n"
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"2: ldw 4(%%sr1,%4),%3\n"
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" subi 32,%2,%2\n"
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" mtctl %2,11\n"
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" vshd %0,%3,%0\n"
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"3: \n"
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
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: "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2)
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: "r" (saddr), "r" (regs->isr) );
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DPRINTF("val = " RFMT "\n", val);
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if (flop)
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((__u32*)(regs->fr))[toreg] = val;
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else if (toreg)
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regs->gr[toreg] = val;
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return ret;
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}
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static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
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{
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unsigned long saddr = regs->ior;
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__u64 val = 0;
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ASM_EXCEPTIONTABLE_VAR(ret);
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DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
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regs->isr, regs->ior, toreg);
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if (!IS_ENABLED(CONFIG_64BIT) && !flop)
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return ERR_NOTHANDLED;
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#ifdef CONFIG_64BIT
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__asm__ __volatile__ (
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" depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */
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" mtsp %4, %%sr1\n"
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" depd %%r0,63,3,%3\n"
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"1: ldd 0(%%sr1,%3),%0\n"
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"2: ldd 8(%%sr1,%3),%%r20\n"
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" subi 64,%%r19,%%r19\n"
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" mtsar %%r19\n"
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" shrpd %0,%%r20,%%sar,%0\n"
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"3: \n"
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
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: "=r" (val), "+r" (ret)
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: "0" (val), "r" (saddr), "r" (regs->isr)
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: "r19", "r20" );
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#else
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{
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unsigned long shift, temp1;
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__asm__ __volatile__ (
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" zdep %2,29,2,%3\n" /* r19=(ofs&3)*8 */
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" mtsp %5, %%sr1\n"
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" dep %%r0,31,2,%2\n"
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"1: ldw 0(%%sr1,%2),%0\n"
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"2: ldw 4(%%sr1,%2),%R0\n"
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"3: ldw 8(%%sr1,%2),%4\n"
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" subi 32,%3,%3\n"
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" mtsar %3\n"
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" vshd %0,%R0,%0\n"
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" vshd %R0,%4,%R0\n"
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"4: \n"
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b)
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: "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
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: "r" (regs->isr) );
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}
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#endif
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DPRINTF("val = 0x%llx\n", val);
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if (flop)
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regs->fr[toreg] = val;
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else if (toreg)
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regs->gr[toreg] = val;
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return ret;
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}
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static int emulate_sth(struct pt_regs *regs, int frreg)
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{
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unsigned long val = regs->gr[frreg], temp1;
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ASM_EXCEPTIONTABLE_VAR(ret);
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if (!frreg)
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val = 0;
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DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
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val, regs->isr, regs->ior);
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__asm__ __volatile__ (
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" mtsp %4, %%sr1\n"
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" extrw,u %2, 23, 8, %1\n"
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"1: stb %1, 0(%%sr1, %3)\n"
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"2: stb %2, 1(%%sr1, %3)\n"
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"3: \n"
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
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: "+r" (ret), "=&r" (temp1)
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: "r" (val), "r" (regs->ior), "r" (regs->isr) );
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return ret;
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}
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static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
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{
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unsigned long val;
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ASM_EXCEPTIONTABLE_VAR(ret);
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if (flop)
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val = ((__u32*)(regs->fr))[frreg];
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else if (frreg)
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val = regs->gr[frreg];
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else
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val = 0;
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DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
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val, regs->isr, regs->ior);
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__asm__ __volatile__ (
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" mtsp %3, %%sr1\n"
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" zdep %2, 28, 2, %%r19\n"
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" dep %%r0, 31, 2, %2\n"
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" mtsar %%r19\n"
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" depwi,z -2, %%sar, 32, %%r19\n"
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"1: ldw 0(%%sr1,%2),%%r20\n"
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"2: ldw 4(%%sr1,%2),%%r21\n"
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" vshd %%r0, %1, %%r22\n"
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" vshd %1, %%r0, %%r1\n"
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" and %%r20, %%r19, %%r20\n"
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" andcm %%r21, %%r19, %%r21\n"
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" or %%r22, %%r20, %%r20\n"
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" or %%r1, %%r21, %%r21\n"
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" stw %%r20,0(%%sr1,%2)\n"
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" stw %%r21,4(%%sr1,%2)\n"
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"3: \n"
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
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: "+r" (ret)
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: "r" (val), "r" (regs->ior), "r" (regs->isr)
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: "r19", "r20", "r21", "r22", "r1" );
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return ret;
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}
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static int emulate_std(struct pt_regs *regs, int frreg, int flop)
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{
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__u64 val;
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ASM_EXCEPTIONTABLE_VAR(ret);
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if (flop)
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val = regs->fr[frreg];
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else if (frreg)
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val = regs->gr[frreg];
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else
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val = 0;
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DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
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val, regs->isr, regs->ior);
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if (!IS_ENABLED(CONFIG_64BIT) && !flop)
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return ERR_NOTHANDLED;
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#ifdef CONFIG_64BIT
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__asm__ __volatile__ (
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" mtsp %3, %%sr1\n"
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" depd,z %2, 60, 3, %%r19\n"
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" depd %%r0, 63, 3, %2\n"
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" mtsar %%r19\n"
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" depdi,z -2, %%sar, 64, %%r19\n"
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"1: ldd 0(%%sr1,%2),%%r20\n"
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"2: ldd 8(%%sr1,%2),%%r21\n"
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" shrpd %%r0, %1, %%sar, %%r22\n"
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" shrpd %1, %%r0, %%sar, %%r1\n"
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" and %%r20, %%r19, %%r20\n"
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" andcm %%r21, %%r19, %%r21\n"
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" or %%r22, %%r20, %%r20\n"
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" or %%r1, %%r21, %%r21\n"
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"3: std %%r20,0(%%sr1,%2)\n"
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"4: std %%r21,8(%%sr1,%2)\n"
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"5: \n"
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b)
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: "+r" (ret)
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: "r" (val), "r" (regs->ior), "r" (regs->isr)
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: "r19", "r20", "r21", "r22", "r1" );
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#else
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{
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unsigned long valh=(val>>32),vall=(val&0xffffffffl);
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__asm__ __volatile__ (
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" mtsp %4, %%sr1\n"
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" zdep %2, 29, 2, %%r19\n"
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" dep %%r0, 31, 2, %3\n"
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" mtsar %%r19\n"
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" zvdepi -2, 32, %%r19\n"
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"1: ldw 0(%%sr1,%3),%%r20\n"
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"2: ldw 8(%%sr1,%3),%%r21\n"
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" vshd %1, %2, %%r1\n"
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" vshd %%r0, %1, %1\n"
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" vshd %2, %%r0, %2\n"
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" and %%r20, %%r19, %%r20\n"
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" andcm %%r21, %%r19, %%r21\n"
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" or %1, %%r20, %1\n"
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" or %2, %%r21, %2\n"
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"3: stw %1,0(%%sr1,%3)\n"
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"4: stw %%r1,4(%%sr1,%3)\n"
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"5: stw %2,8(%%sr1,%3)\n"
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"6: \n"
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b)
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ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b)
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: "+r" (ret)
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: "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr)
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: "r19", "r20", "r21", "r1" );
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}
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#endif
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return ret;
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}
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void handle_unaligned(struct pt_regs *regs)
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{
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static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
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unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
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int modify = 0;
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int ret = ERR_NOTHANDLED;
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__inc_irq_stat(irq_unaligned_count);
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/* log a message with pacing */
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if (user_mode(regs)) {
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if (current->thread.flags & PARISC_UAC_SIGBUS) {
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goto force_sigbus;
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}
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if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
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__ratelimit(&ratelimit)) {
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printk(KERN_WARNING "%s(%d): unaligned access to " RFMT
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" at ip " RFMT " (iir " RFMT ")\n",
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current->comm, task_pid_nr(current), regs->ior,
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regs->iaoq[0], regs->iir);
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#ifdef DEBUG_UNALIGNED
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show_regs(regs);
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#endif
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}
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|
|
|
if (!unaligned_enabled)
|
|
goto force_sigbus;
|
|
}
|
|
|
|
/* handle modification - OK, it's ugly, see the instruction manual */
|
|
switch (MAJOR_OP(regs->iir))
|
|
{
|
|
case 0x03:
|
|
case 0x09:
|
|
case 0x0b:
|
|
if (regs->iir&0x20)
|
|
{
|
|
modify = 1;
|
|
if (regs->iir&0x1000) /* short loads */
|
|
if (regs->iir&0x200)
|
|
newbase += IM5_3(regs->iir);
|
|
else
|
|
newbase += IM5_2(regs->iir);
|
|
else if (regs->iir&0x2000) /* scaled indexed */
|
|
{
|
|
int shift=0;
|
|
switch (regs->iir & OPCODE1_MASK)
|
|
{
|
|
case OPCODE_LDH_I:
|
|
shift= 1; break;
|
|
case OPCODE_LDW_I:
|
|
shift= 2; break;
|
|
case OPCODE_LDD_I:
|
|
case OPCODE_LDDA_I:
|
|
shift= 3; break;
|
|
}
|
|
newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
|
|
} else /* simple indexed */
|
|
newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
|
|
}
|
|
break;
|
|
case 0x13:
|
|
case 0x1b:
|
|
modify = 1;
|
|
newbase += IM14(regs->iir);
|
|
break;
|
|
case 0x14:
|
|
case 0x1c:
|
|
if (regs->iir&8)
|
|
{
|
|
modify = 1;
|
|
newbase += IM14(regs->iir&~0xe);
|
|
}
|
|
break;
|
|
case 0x16:
|
|
case 0x1e:
|
|
modify = 1;
|
|
newbase += IM14(regs->iir&6);
|
|
break;
|
|
case 0x17:
|
|
case 0x1f:
|
|
if (regs->iir&4)
|
|
{
|
|
modify = 1;
|
|
newbase += IM14(regs->iir&~4);
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* TODO: make this cleaner... */
|
|
switch (regs->iir & OPCODE1_MASK)
|
|
{
|
|
case OPCODE_LDH_I:
|
|
case OPCODE_LDH_S:
|
|
ret = emulate_ldh(regs, R3(regs->iir));
|
|
break;
|
|
|
|
case OPCODE_LDW_I:
|
|
case OPCODE_LDWA_I:
|
|
case OPCODE_LDW_S:
|
|
case OPCODE_LDWA_S:
|
|
ret = emulate_ldw(regs, R3(regs->iir),0);
|
|
break;
|
|
|
|
case OPCODE_STH:
|
|
ret = emulate_sth(regs, R2(regs->iir));
|
|
break;
|
|
|
|
case OPCODE_STW:
|
|
case OPCODE_STWA:
|
|
ret = emulate_stw(regs, R2(regs->iir),0);
|
|
break;
|
|
|
|
#ifdef CONFIG_64BIT
|
|
case OPCODE_LDD_I:
|
|
case OPCODE_LDDA_I:
|
|
case OPCODE_LDD_S:
|
|
case OPCODE_LDDA_S:
|
|
ret = emulate_ldd(regs, R3(regs->iir),0);
|
|
break;
|
|
|
|
case OPCODE_STD:
|
|
case OPCODE_STDA:
|
|
ret = emulate_std(regs, R2(regs->iir),0);
|
|
break;
|
|
#endif
|
|
|
|
case OPCODE_FLDWX:
|
|
case OPCODE_FLDWS:
|
|
case OPCODE_FLDWXR:
|
|
case OPCODE_FLDWSR:
|
|
ret = emulate_ldw(regs,FR3(regs->iir),1);
|
|
break;
|
|
|
|
case OPCODE_FLDDX:
|
|
case OPCODE_FLDDS:
|
|
ret = emulate_ldd(regs,R3(regs->iir),1);
|
|
break;
|
|
|
|
case OPCODE_FSTWX:
|
|
case OPCODE_FSTWS:
|
|
case OPCODE_FSTWXR:
|
|
case OPCODE_FSTWSR:
|
|
ret = emulate_stw(regs,FR3(regs->iir),1);
|
|
break;
|
|
|
|
case OPCODE_FSTDX:
|
|
case OPCODE_FSTDS:
|
|
ret = emulate_std(regs,R3(regs->iir),1);
|
|
break;
|
|
|
|
case OPCODE_LDCD_I:
|
|
case OPCODE_LDCW_I:
|
|
case OPCODE_LDCD_S:
|
|
case OPCODE_LDCW_S:
|
|
ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */
|
|
break;
|
|
}
|
|
switch (regs->iir & OPCODE2_MASK)
|
|
{
|
|
case OPCODE_FLDD_L:
|
|
ret = emulate_ldd(regs,R2(regs->iir),1);
|
|
break;
|
|
case OPCODE_FSTD_L:
|
|
ret = emulate_std(regs, R2(regs->iir),1);
|
|
break;
|
|
#ifdef CONFIG_64BIT
|
|
case OPCODE_LDD_L:
|
|
ret = emulate_ldd(regs, R2(regs->iir),0);
|
|
break;
|
|
case OPCODE_STD_L:
|
|
ret = emulate_std(regs, R2(regs->iir),0);
|
|
break;
|
|
#endif
|
|
}
|
|
switch (regs->iir & OPCODE3_MASK)
|
|
{
|
|
case OPCODE_FLDW_L:
|
|
ret = emulate_ldw(regs, R2(regs->iir), 1);
|
|
break;
|
|
case OPCODE_LDW_M:
|
|
ret = emulate_ldw(regs, R2(regs->iir), 0);
|
|
break;
|
|
|
|
case OPCODE_FSTW_L:
|
|
ret = emulate_stw(regs, R2(regs->iir),1);
|
|
break;
|
|
case OPCODE_STW_M:
|
|
ret = emulate_stw(regs, R2(regs->iir),0);
|
|
break;
|
|
}
|
|
switch (regs->iir & OPCODE4_MASK)
|
|
{
|
|
case OPCODE_LDH_L:
|
|
ret = emulate_ldh(regs, R2(regs->iir));
|
|
break;
|
|
case OPCODE_LDW_L:
|
|
case OPCODE_LDWM:
|
|
ret = emulate_ldw(regs, R2(regs->iir),0);
|
|
break;
|
|
case OPCODE_STH_L:
|
|
ret = emulate_sth(regs, R2(regs->iir));
|
|
break;
|
|
case OPCODE_STW_L:
|
|
case OPCODE_STWM:
|
|
ret = emulate_stw(regs, R2(regs->iir),0);
|
|
break;
|
|
}
|
|
|
|
if (ret == 0 && modify && R1(regs->iir))
|
|
regs->gr[R1(regs->iir)] = newbase;
|
|
|
|
|
|
if (ret == ERR_NOTHANDLED)
|
|
printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
|
|
|
|
DPRINTF("ret = %d\n", ret);
|
|
|
|
if (ret)
|
|
{
|
|
/*
|
|
* The unaligned handler failed.
|
|
* If we were called by __get_user() or __put_user() jump
|
|
* to it's exception fixup handler instead of crashing.
|
|
*/
|
|
if (!user_mode(regs) && fixup_exception(regs))
|
|
return;
|
|
|
|
printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
|
|
die_if_kernel("Unaligned data reference", regs, 28);
|
|
|
|
if (ret == -EFAULT)
|
|
{
|
|
force_sig_fault(SIGSEGV, SEGV_MAPERR,
|
|
(void __user *)regs->ior);
|
|
}
|
|
else
|
|
{
|
|
force_sigbus:
|
|
/* couldn't handle it ... */
|
|
force_sig_fault(SIGBUS, BUS_ADRALN,
|
|
(void __user *)regs->ior);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
/* else we handled it, let life go on. */
|
|
regs->gr[0]|=PSW_N;
|
|
}
|
|
|
|
/*
|
|
* NB: check_unaligned() is only used for PCXS processors right
|
|
* now, so we only check for PA1.1 encodings at this point.
|
|
*/
|
|
|
|
int
|
|
check_unaligned(struct pt_regs *regs)
|
|
{
|
|
unsigned long align_mask;
|
|
|
|
/* Get alignment mask */
|
|
|
|
align_mask = 0UL;
|
|
switch (regs->iir & OPCODE1_MASK) {
|
|
|
|
case OPCODE_LDH_I:
|
|
case OPCODE_LDH_S:
|
|
case OPCODE_STH:
|
|
align_mask = 1UL;
|
|
break;
|
|
|
|
case OPCODE_LDW_I:
|
|
case OPCODE_LDWA_I:
|
|
case OPCODE_LDW_S:
|
|
case OPCODE_LDWA_S:
|
|
case OPCODE_STW:
|
|
case OPCODE_STWA:
|
|
align_mask = 3UL;
|
|
break;
|
|
|
|
default:
|
|
switch (regs->iir & OPCODE4_MASK) {
|
|
case OPCODE_LDH_L:
|
|
case OPCODE_STH_L:
|
|
align_mask = 1UL;
|
|
break;
|
|
case OPCODE_LDW_L:
|
|
case OPCODE_LDWM:
|
|
case OPCODE_STW_L:
|
|
case OPCODE_STWM:
|
|
align_mask = 3UL;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
return (int)(regs->ior & align_mask);
|
|
}
|
|
|