148 lines
3.0 KiB
Plaintext
148 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* a4m072 board Device Tree Source
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*
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* Copyright (C) 2011 DENX Software Engineering GmbH
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* Heiko Schocher <hs@denx.de>
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*
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* Copyright (C) 2007 Semihalf
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* Marian Balakowicz <m8@semihalf.com>
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*/
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/include/ "mpc5200b.dtsi"
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&gpt0 { fsl,has-wdt; };
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&gpt3 { gpio-controller; };
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&gpt4 { gpio-controller; };
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&gpt5 { gpio-controller; };
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/ {
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model = "anonymous,a4m072";
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compatible = "anonymous,a4m072";
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soc5200@f0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc5200b-immr";
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ranges = <0 0xf0000000 0x0000c000>;
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reg = <0xf0000000 0x00000100>;
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bus-frequency = <0>; /* From boot loader */
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system-frequency = <0>; /* From boot loader */
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cdm@200 {
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fsl,init-ext-48mhz-en = <0x0>;
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fsl,init-fd-enable = <0x01>;
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fsl,init-fd-counters = <0x3333>;
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};
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spi@f00 {
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status = "disabled";
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};
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psc@2000 {
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2000 0x100>;
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interrupts = <2 1 0>;
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};
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psc@2200 {
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2200 0x100>;
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interrupts = <2 2 0>;
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};
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psc@2400 {
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2400 0x100>;
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interrupts = <2 3 0>;
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};
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psc@2600 {
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status = "disabled";
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};
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psc@2800 {
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status = "disabled";
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};
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psc@2c00 {
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2c00 0x100>;
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interrupts = <2 4 0>;
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};
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ethernet@3000 {
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phy-handle = <&phy0>;
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};
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mdio@3000 {
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phy0: ethernet-phy@1f {
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reg = <0x1f>;
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interrupts = <1 2 0>; /* IRQ 2 active low */
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};
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};
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i2c@3d00 {
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status = "disabled";
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};
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i2c@3d40 {
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hwmon@2e {
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compatible = "nsc,lm87";
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reg = <0x2e>;
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};
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rtc@51 {
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compatible = "nxp,rtc8564";
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reg = <0x51>;
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};
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};
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};
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localbus {
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compatible = "fsl,mpc5200b-lpb","simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0xfe000000 0x02000000
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1 0 0x62000000 0x00400000
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2 0 0x64000000 0x00200000
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3 0 0x66000000 0x01000000
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6 0 0x68000000 0x01000000
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7 0 0x6a000000 0x00000004>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x02000000>;
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bank-width = <2>;
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#size-cells = <1>;
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#address-cells = <1>;
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};
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sram0@1,0 {
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compatible = "mtd-ram";
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reg = <1 0x00000 0x00400000>;
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bank-width = <2>;
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};
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};
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pci@f0000d00 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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compatible = "fsl,mpc5200-pci";
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reg = <0xf0000d00 0x100>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x16 */
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0xc000 0 0 1 &mpc5200_pic 1 3 3
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0xc000 0 0 2 &mpc5200_pic 1 3 3
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0xc000 0 0 3 &mpc5200_pic 1 3 3
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0xc000 0 0 4 &mpc5200_pic 1 3 3>;
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clock-frequency = <0>; /* From boot loader */
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interrupts = <2 8 0 2 9 0 2 10 0>;
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bus-range = <0 0>;
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ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000>,
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<0x02000000 0 0x90000000 0x90000000 0 0x10000000>,
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<0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
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};
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};
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