320 lines
7.4 KiB
Plaintext
320 lines
7.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* P1021 MDS Device Tree Source
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*
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* Copyright 2010,2012 Freescale Semiconductor Inc.
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*/
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/include/ "p1021si-pre.dtsi"
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/ {
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model = "fsl,P1021";
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compatible = "fsl,P1021MDS";
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aliases {
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ethernet3 = &enet3;
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ethernet4 = &enet4;
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};
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memory {
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device_type = "memory";
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};
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lbc: localbus@ffe05000 {
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reg = <0x0 0xffe05000 0x0 0x1000>;
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/* NAND Flash, BCSR, PMC0/1*/
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ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
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0x1 0x0 0x0 0xf8000000 0x00008000
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0x2 0x0 0x0 0xf8010000 0x00020000
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0x3 0x0 0x0 0xf8020000 0x00020000>;
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nand@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p1021-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x0 0x0 0x40000>;
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partition@0 {
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/* This location must not be altered */
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/* 1MB for u-boot Bootloader Image */
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reg = <0x0 0x00100000>;
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label = "NAND (RO) U-Boot Image";
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read-only;
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};
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partition@100000 {
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/* 1MB for DTB Image */
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reg = <0x00100000 0x00100000>;
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label = "NAND (RO) DTB Image";
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read-only;
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};
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partition@200000 {
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/* 4MB for Linux Kernel Image */
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reg = <0x00200000 0x00400000>;
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label = "NAND (RO) Linux Kernel Image";
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read-only;
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};
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partition@600000 {
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/* 5MB for Compressed Root file System Image */
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reg = <0x00600000 0x00500000>;
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label = "NAND (RO) Compressed RFS Image";
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read-only;
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};
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partition@b00000 {
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/* 6MB for JFFS2 based Root file System */
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reg = <0x00a00000 0x00600000>;
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label = "NAND (RW) JFFS2 Root File System";
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};
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partition@1100000 {
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/* 14MB for JFFS2 based Root file System */
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reg = <0x01100000 0x00e00000>;
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label = "NAND (RW) Writable User area";
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};
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partition@1f00000 {
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/* 1MB for microcode */
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reg = <0x01f00000 0x00100000>;
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label = "NAND (RO) QE Ucode";
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read-only;
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};
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};
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bcsr@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p1021mds-bcsr";
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reg = <1 0 0x8000>;
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ranges = <0 1 0 0x8000>;
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};
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pib@2,0 {
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compatible = "fsl,p1021mds-pib";
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reg = <2 0 0x10000>;
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};
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pib@3,0 {
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compatible = "fsl,p1021mds-pib";
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reg = <3 0 0x10000>;
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};
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};
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soc: soc@ffe00000 {
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compatible = "fsl,p1021-immr", "simple-bus";
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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i2c@3000 {
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rtc@68 {
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compatible = "dallas,ds1374";
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reg = <0x68>;
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};
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};
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spi@7000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25sl12801", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>; /* input clock */
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partition@u-boot {
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label = "u-boot-spi";
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reg = <0x00000000 0x00100000>;
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read-only;
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};
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partition@kernel {
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label = "kernel-spi";
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reg = <0x00100000 0x00500000>;
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read-only;
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};
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partition@dtb {
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label = "dtb-spi";
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reg = <0x00600000 0x00100000>;
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read-only;
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};
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partition@fs {
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label = "file system-spi";
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reg = <0x00700000 0x00900000>;
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};
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};
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};
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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mdio@24000 {
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phy0: ethernet-phy@0 {
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interrupts = <1 1 0 0>;
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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interrupts = <2 1 0 0>;
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reg = <0x1>;
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};
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phy4: ethernet-phy@4 {
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reg = <0x4>;
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};
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tbi-phy@5 {
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device_type = "tbi-phy";
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reg = <0x5>;
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};
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};
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mdio@25000 {
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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ethernet@b0000 {
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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ethernet@b1000 {
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phy-handle = <&phy4>;
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tbi-handle = <&tbi0>;
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phy-connection-type = "sgmii";
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};
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ethernet@b2000 {
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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par_io@e0100 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xe0100 0x60>;
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ranges = <0x0 0xe0100 0x60>;
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device_type = "par_io";
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num-ports = <3>;
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pio1: ucc_pin@1 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
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0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
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0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
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0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
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0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
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0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
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0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
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0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
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0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
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0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
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0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
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0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
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0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
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0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
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0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
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0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
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0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
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};
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pio2: ucc_pin@2 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
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0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
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0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
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0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
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0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
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0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
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0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
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0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
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0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
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};
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};
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};
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pci0: pcie@ffe09000 {
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reg = <0 0xffe09000 0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@ffe0a000 {
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reg = <0 0xffe0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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qe: qe@ffe80000 {
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ranges = <0x0 0x0 0xffe80000 0x40000>;
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reg = <0 0xffe80000 0 0x480>;
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brg-frequency = <0>;
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bus-frequency = <0>;
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status = "disabled"; /* no firmware loaded */
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enet3: ucc@2000 {
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device_type = "network";
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compatible = "ucc_geth";
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "clk12";
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tx-clock-name = "clk9";
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pio-handle = <&pio1>;
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phy-handle = <&qe_phy0>;
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phy-connection-type = "mii";
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};
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mdio@2120 {
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qe_phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <4 1 0 0>;
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reg = <0x0>;
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};
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qe_phy1: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1 0 0>;
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reg = <0x3>;
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};
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tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet4: ucc@2400 {
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device_type = "network";
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compatible = "ucc_geth";
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk13";
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pio-handle = <&pio2>;
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phy-handle = <&qe_phy1>;
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phy-connection-type = "rmii";
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};
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};
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};
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/include/ "p1021si-post.dtsi"
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