501 lines
12 KiB
C
501 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2008 Michael Ellerman, IBM Corporation.
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*/
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#include <linux/kprobes.h>
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#include <linux/mmu_context.h>
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#include <linux/random.h>
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#include <linux/vmalloc.h>
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#include <linux/init.h>
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#include <linux/cpuhotplug.h>
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#include <linux/uaccess.h>
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#include <linux/jump_label.h>
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#include <asm/debug.h>
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#include <asm/pgalloc.h>
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#include <asm/tlb.h>
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#include <asm/tlbflush.h>
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#include <asm/page.h>
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#include <asm/code-patching.h>
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#include <asm/inst.h>
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static int __patch_instruction(u32 *exec_addr, ppc_inst_t instr, u32 *patch_addr)
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{
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if (!ppc_inst_prefixed(instr)) {
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u32 val = ppc_inst_val(instr);
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__put_kernel_nofault(patch_addr, &val, u32, failed);
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} else {
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u64 val = ppc_inst_as_ulong(instr);
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__put_kernel_nofault(patch_addr, &val, u64, failed);
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}
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asm ("dcbst 0, %0; sync; icbi 0,%1; sync; isync" :: "r" (patch_addr),
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"r" (exec_addr));
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return 0;
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failed:
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return -EPERM;
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}
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int raw_patch_instruction(u32 *addr, ppc_inst_t instr)
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{
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return __patch_instruction(addr, instr, addr);
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}
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struct patch_context {
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union {
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struct vm_struct *area;
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struct mm_struct *mm;
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};
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unsigned long addr;
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pte_t *pte;
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};
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static DEFINE_PER_CPU(struct patch_context, cpu_patching_context);
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static int map_patch_area(void *addr, unsigned long text_poke_addr);
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static void unmap_patch_area(unsigned long addr);
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static bool mm_patch_enabled(void)
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{
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return IS_ENABLED(CONFIG_SMP) && radix_enabled();
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}
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/*
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* The following applies for Radix MMU. Hash MMU has different requirements,
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* and so is not supported.
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*
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* Changing mm requires context synchronising instructions on both sides of
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* the context switch, as well as a hwsync between the last instruction for
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* which the address of an associated storage access was translated using
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* the current context.
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*
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* switch_mm_irqs_off() performs an isync after the context switch. It is
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* the responsibility of the caller to perform the CSI and hwsync before
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* starting/stopping the temp mm.
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*/
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static struct mm_struct *start_using_temp_mm(struct mm_struct *temp_mm)
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{
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struct mm_struct *orig_mm = current->active_mm;
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lockdep_assert_irqs_disabled();
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switch_mm_irqs_off(orig_mm, temp_mm, current);
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WARN_ON(!mm_is_thread_local(temp_mm));
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suspend_breakpoints();
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return orig_mm;
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}
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static void stop_using_temp_mm(struct mm_struct *temp_mm,
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struct mm_struct *orig_mm)
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{
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lockdep_assert_irqs_disabled();
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switch_mm_irqs_off(temp_mm, orig_mm, current);
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restore_breakpoints();
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}
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static int text_area_cpu_up(unsigned int cpu)
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{
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struct vm_struct *area;
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unsigned long addr;
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int err;
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area = get_vm_area(PAGE_SIZE, VM_ALLOC);
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if (!area) {
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WARN_ONCE(1, "Failed to create text area for cpu %d\n",
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cpu);
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return -1;
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}
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// Map/unmap the area to ensure all page tables are pre-allocated
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addr = (unsigned long)area->addr;
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err = map_patch_area(empty_zero_page, addr);
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if (err)
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return err;
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unmap_patch_area(addr);
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this_cpu_write(cpu_patching_context.area, area);
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this_cpu_write(cpu_patching_context.addr, addr);
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this_cpu_write(cpu_patching_context.pte, virt_to_kpte(addr));
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return 0;
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}
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static int text_area_cpu_down(unsigned int cpu)
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{
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free_vm_area(this_cpu_read(cpu_patching_context.area));
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this_cpu_write(cpu_patching_context.area, NULL);
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this_cpu_write(cpu_patching_context.addr, 0);
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this_cpu_write(cpu_patching_context.pte, NULL);
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return 0;
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}
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static void put_patching_mm(struct mm_struct *mm, unsigned long patching_addr)
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{
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struct mmu_gather tlb;
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tlb_gather_mmu(&tlb, mm);
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free_pgd_range(&tlb, patching_addr, patching_addr + PAGE_SIZE, 0, 0);
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mmput(mm);
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}
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static int text_area_cpu_up_mm(unsigned int cpu)
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{
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struct mm_struct *mm;
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unsigned long addr;
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pte_t *pte;
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spinlock_t *ptl;
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mm = mm_alloc();
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if (WARN_ON(!mm))
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goto fail_no_mm;
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/*
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* Choose a random page-aligned address from the interval
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* [PAGE_SIZE .. DEFAULT_MAP_WINDOW - PAGE_SIZE].
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* The lower address bound is PAGE_SIZE to avoid the zero-page.
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*/
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addr = (1 + (get_random_long() % (DEFAULT_MAP_WINDOW / PAGE_SIZE - 2))) << PAGE_SHIFT;
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/*
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* PTE allocation uses GFP_KERNEL which means we need to
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* pre-allocate the PTE here because we cannot do the
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* allocation during patching when IRQs are disabled.
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*
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* Using get_locked_pte() to avoid open coding, the lock
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* is unnecessary.
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*/
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pte = get_locked_pte(mm, addr, &ptl);
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if (!pte)
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goto fail_no_pte;
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pte_unmap_unlock(pte, ptl);
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this_cpu_write(cpu_patching_context.mm, mm);
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this_cpu_write(cpu_patching_context.addr, addr);
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return 0;
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fail_no_pte:
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put_patching_mm(mm, addr);
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fail_no_mm:
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return -ENOMEM;
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}
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static int text_area_cpu_down_mm(unsigned int cpu)
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{
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put_patching_mm(this_cpu_read(cpu_patching_context.mm),
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this_cpu_read(cpu_patching_context.addr));
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this_cpu_write(cpu_patching_context.mm, NULL);
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this_cpu_write(cpu_patching_context.addr, 0);
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return 0;
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}
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static __ro_after_init DEFINE_STATIC_KEY_FALSE(poking_init_done);
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void __init poking_init(void)
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{
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int ret;
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if (!IS_ENABLED(CONFIG_STRICT_KERNEL_RWX))
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return;
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if (mm_patch_enabled())
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ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
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"powerpc/text_poke_mm:online",
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text_area_cpu_up_mm,
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text_area_cpu_down_mm);
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else
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ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
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"powerpc/text_poke:online",
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text_area_cpu_up,
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text_area_cpu_down);
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/* cpuhp_setup_state returns >= 0 on success */
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if (WARN_ON(ret < 0))
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return;
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static_branch_enable(&poking_init_done);
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}
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static unsigned long get_patch_pfn(void *addr)
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{
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if (IS_ENABLED(CONFIG_MODULES) && is_vmalloc_or_module_addr(addr))
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return vmalloc_to_pfn(addr);
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else
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return __pa_symbol(addr) >> PAGE_SHIFT;
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}
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/*
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* This can be called for kernel text or a module.
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*/
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static int map_patch_area(void *addr, unsigned long text_poke_addr)
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{
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unsigned long pfn = get_patch_pfn(addr);
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return map_kernel_page(text_poke_addr, (pfn << PAGE_SHIFT), PAGE_KERNEL);
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}
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static void unmap_patch_area(unsigned long addr)
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{
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pte_t *ptep;
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pmd_t *pmdp;
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pud_t *pudp;
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p4d_t *p4dp;
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pgd_t *pgdp;
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pgdp = pgd_offset_k(addr);
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if (WARN_ON(pgd_none(*pgdp)))
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return;
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p4dp = p4d_offset(pgdp, addr);
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if (WARN_ON(p4d_none(*p4dp)))
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return;
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pudp = pud_offset(p4dp, addr);
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if (WARN_ON(pud_none(*pudp)))
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return;
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pmdp = pmd_offset(pudp, addr);
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if (WARN_ON(pmd_none(*pmdp)))
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return;
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ptep = pte_offset_kernel(pmdp, addr);
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if (WARN_ON(pte_none(*ptep)))
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return;
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/*
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* In hash, pte_clear flushes the tlb, in radix, we have to
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*/
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pte_clear(&init_mm, addr, ptep);
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flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
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}
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static int __do_patch_instruction_mm(u32 *addr, ppc_inst_t instr)
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{
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int err;
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u32 *patch_addr;
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unsigned long text_poke_addr;
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pte_t *pte;
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unsigned long pfn = get_patch_pfn(addr);
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struct mm_struct *patching_mm;
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struct mm_struct *orig_mm;
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spinlock_t *ptl;
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patching_mm = __this_cpu_read(cpu_patching_context.mm);
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text_poke_addr = __this_cpu_read(cpu_patching_context.addr);
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patch_addr = (u32 *)(text_poke_addr + offset_in_page(addr));
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pte = get_locked_pte(patching_mm, text_poke_addr, &ptl);
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if (!pte)
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return -ENOMEM;
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__set_pte_at(patching_mm, text_poke_addr, pte, pfn_pte(pfn, PAGE_KERNEL), 0);
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/* order PTE update before use, also serves as the hwsync */
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asm volatile("ptesync": : :"memory");
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/* order context switch after arbitrary prior code */
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isync();
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orig_mm = start_using_temp_mm(patching_mm);
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err = __patch_instruction(addr, instr, patch_addr);
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/* hwsync performed by __patch_instruction (sync) if successful */
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if (err)
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mb(); /* sync */
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/* context synchronisation performed by __patch_instruction (isync or exception) */
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stop_using_temp_mm(patching_mm, orig_mm);
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pte_clear(patching_mm, text_poke_addr, pte);
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/*
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* ptesync to order PTE update before TLB invalidation done
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* by radix__local_flush_tlb_page_psize (in _tlbiel_va)
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*/
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local_flush_tlb_page_psize(patching_mm, text_poke_addr, mmu_virtual_psize);
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pte_unmap_unlock(pte, ptl);
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return err;
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}
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static int __do_patch_instruction(u32 *addr, ppc_inst_t instr)
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{
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int err;
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u32 *patch_addr;
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unsigned long text_poke_addr;
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pte_t *pte;
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unsigned long pfn = get_patch_pfn(addr);
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text_poke_addr = (unsigned long)__this_cpu_read(cpu_patching_context.addr) & PAGE_MASK;
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patch_addr = (u32 *)(text_poke_addr + offset_in_page(addr));
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pte = __this_cpu_read(cpu_patching_context.pte);
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__set_pte_at(&init_mm, text_poke_addr, pte, pfn_pte(pfn, PAGE_KERNEL), 0);
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/* See ptesync comment in radix__set_pte_at() */
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if (radix_enabled())
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asm volatile("ptesync": : :"memory");
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err = __patch_instruction(addr, instr, patch_addr);
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pte_clear(&init_mm, text_poke_addr, pte);
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flush_tlb_kernel_range(text_poke_addr, text_poke_addr + PAGE_SIZE);
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return err;
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}
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int patch_instruction(u32 *addr, ppc_inst_t instr)
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{
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int err;
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unsigned long flags;
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/*
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* During early early boot patch_instruction is called
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* when text_poke_area is not ready, but we still need
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* to allow patching. We just do the plain old patching
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*/
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if (!IS_ENABLED(CONFIG_STRICT_KERNEL_RWX) ||
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!static_branch_likely(&poking_init_done))
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return raw_patch_instruction(addr, instr);
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local_irq_save(flags);
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if (mm_patch_enabled())
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err = __do_patch_instruction_mm(addr, instr);
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else
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err = __do_patch_instruction(addr, instr);
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local_irq_restore(flags);
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return err;
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}
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NOKPROBE_SYMBOL(patch_instruction);
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int patch_branch(u32 *addr, unsigned long target, int flags)
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{
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ppc_inst_t instr;
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if (create_branch(&instr, addr, target, flags))
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return -ERANGE;
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return patch_instruction(addr, instr);
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}
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/*
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* Helper to check if a given instruction is a conditional branch
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* Derived from the conditional checks in analyse_instr()
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*/
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bool is_conditional_branch(ppc_inst_t instr)
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{
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unsigned int opcode = ppc_inst_primary_opcode(instr);
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if (opcode == 16) /* bc, bca, bcl, bcla */
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return true;
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if (opcode == 19) {
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switch ((ppc_inst_val(instr) >> 1) & 0x3ff) {
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case 16: /* bclr, bclrl */
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case 528: /* bcctr, bcctrl */
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case 560: /* bctar, bctarl */
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return true;
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}
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}
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return false;
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}
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NOKPROBE_SYMBOL(is_conditional_branch);
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int create_cond_branch(ppc_inst_t *instr, const u32 *addr,
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unsigned long target, int flags)
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{
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long offset;
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offset = target;
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if (! (flags & BRANCH_ABSOLUTE))
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offset = offset - (unsigned long)addr;
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/* Check we can represent the target in the instruction format */
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if (!is_offset_in_cond_branch_range(offset))
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return 1;
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/* Mask out the flags and target, so they don't step on each other. */
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*instr = ppc_inst(0x40000000 | (flags & 0x3FF0003) | (offset & 0xFFFC));
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return 0;
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}
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int instr_is_relative_branch(ppc_inst_t instr)
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{
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if (ppc_inst_val(instr) & BRANCH_ABSOLUTE)
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return 0;
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return instr_is_branch_iform(instr) || instr_is_branch_bform(instr);
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}
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int instr_is_relative_link_branch(ppc_inst_t instr)
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{
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return instr_is_relative_branch(instr) && (ppc_inst_val(instr) & BRANCH_SET_LINK);
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}
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static unsigned long branch_iform_target(const u32 *instr)
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{
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signed long imm;
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imm = ppc_inst_val(ppc_inst_read(instr)) & 0x3FFFFFC;
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/* If the top bit of the immediate value is set this is negative */
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if (imm & 0x2000000)
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imm -= 0x4000000;
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if ((ppc_inst_val(ppc_inst_read(instr)) & BRANCH_ABSOLUTE) == 0)
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imm += (unsigned long)instr;
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return (unsigned long)imm;
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}
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static unsigned long branch_bform_target(const u32 *instr)
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{
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signed long imm;
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imm = ppc_inst_val(ppc_inst_read(instr)) & 0xFFFC;
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/* If the top bit of the immediate value is set this is negative */
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if (imm & 0x8000)
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imm -= 0x10000;
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if ((ppc_inst_val(ppc_inst_read(instr)) & BRANCH_ABSOLUTE) == 0)
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imm += (unsigned long)instr;
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return (unsigned long)imm;
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}
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unsigned long branch_target(const u32 *instr)
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{
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if (instr_is_branch_iform(ppc_inst_read(instr)))
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return branch_iform_target(instr);
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else if (instr_is_branch_bform(ppc_inst_read(instr)))
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return branch_bform_target(instr);
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return 0;
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}
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int translate_branch(ppc_inst_t *instr, const u32 *dest, const u32 *src)
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{
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unsigned long target;
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target = branch_target(src);
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if (instr_is_branch_iform(ppc_inst_read(src)))
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return create_branch(instr, dest, target,
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ppc_inst_val(ppc_inst_read(src)));
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else if (instr_is_branch_bform(ppc_inst_read(src)))
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return create_cond_branch(instr, dest, target,
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ppc_inst_val(ppc_inst_read(src)));
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return 1;
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}
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