323 lines
8.4 KiB
C
323 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* spu_restore.c
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*
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* (C) Copyright IBM Corp. 2005
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*
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* SPU-side context restore sequence outlined in
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* Synergistic Processor Element Book IV
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*
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* Author: Mark Nutter <mnutter@us.ibm.com>
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*/
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#ifndef LS_SIZE
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#define LS_SIZE 0x40000 /* 256K (in bytes) */
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#endif
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typedef unsigned int u32;
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typedef unsigned long long u64;
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#include <spu_intrinsics.h>
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#include <asm/spu_csa.h>
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#include "spu_utils.h"
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#define BR_INSTR 0x327fff80 /* br -4 */
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#define NOP_INSTR 0x40200000 /* nop */
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#define HEQ_INSTR 0x7b000000 /* heq $0, $0 */
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#define STOP_INSTR 0x00000000 /* stop 0x0 */
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#define ILLEGAL_INSTR 0x00800000 /* illegal instr */
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#define RESTORE_COMPLETE 0x00003ffc /* stop 0x3ffc */
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static inline void fetch_regs_from_mem(addr64 lscsa_ea)
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{
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unsigned int ls = (unsigned int)®s_spill[0];
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unsigned int size = sizeof(regs_spill);
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unsigned int tag_id = 0;
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unsigned int cmd = 0x40; /* GET */
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spu_writech(MFC_LSA, ls);
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spu_writech(MFC_EAH, lscsa_ea.ui[0]);
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spu_writech(MFC_EAL, lscsa_ea.ui[1]);
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spu_writech(MFC_Size, size);
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spu_writech(MFC_TagID, tag_id);
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spu_writech(MFC_Cmd, cmd);
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}
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static inline void restore_upper_240kb(addr64 lscsa_ea)
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{
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unsigned int ls = 16384;
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unsigned int list = (unsigned int)&dma_list[0];
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unsigned int size = sizeof(dma_list);
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unsigned int tag_id = 0;
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unsigned int cmd = 0x44; /* GETL */
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/* Restore, Step 4:
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* Enqueue the GETL command (tag 0) to the MFC SPU command
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* queue to transfer the upper 240 kb of LS from CSA.
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*/
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spu_writech(MFC_LSA, ls);
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spu_writech(MFC_EAH, lscsa_ea.ui[0]);
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spu_writech(MFC_EAL, list);
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spu_writech(MFC_Size, size);
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spu_writech(MFC_TagID, tag_id);
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spu_writech(MFC_Cmd, cmd);
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}
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static inline void restore_decr(void)
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{
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unsigned int offset;
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unsigned int decr_running;
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unsigned int decr;
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/* Restore, Step 6(moved):
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* If the LSCSA "decrementer running" flag is set
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* then write the SPU_WrDec channel with the
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* decrementer value from LSCSA.
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*/
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offset = LSCSA_QW_OFFSET(decr_status);
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decr_running = regs_spill[offset].slot[0] & SPU_DECR_STATUS_RUNNING;
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if (decr_running) {
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offset = LSCSA_QW_OFFSET(decr);
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decr = regs_spill[offset].slot[0];
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spu_writech(SPU_WrDec, decr);
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}
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}
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static inline void write_ppu_mb(void)
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{
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unsigned int offset;
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unsigned int data;
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/* Restore, Step 11:
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* Write the MFC_WrOut_MB channel with the PPU_MB
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* data from LSCSA.
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*/
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offset = LSCSA_QW_OFFSET(ppu_mb);
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data = regs_spill[offset].slot[0];
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spu_writech(SPU_WrOutMbox, data);
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}
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static inline void write_ppuint_mb(void)
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{
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unsigned int offset;
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unsigned int data;
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/* Restore, Step 12:
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* Write the MFC_WrInt_MB channel with the PPUINT_MB
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* data from LSCSA.
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*/
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offset = LSCSA_QW_OFFSET(ppuint_mb);
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data = regs_spill[offset].slot[0];
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spu_writech(SPU_WrOutIntrMbox, data);
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}
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static inline void restore_fpcr(void)
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{
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unsigned int offset;
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vector unsigned int fpcr;
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/* Restore, Step 13:
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* Restore the floating-point status and control
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* register from the LSCSA.
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*/
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offset = LSCSA_QW_OFFSET(fpcr);
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fpcr = regs_spill[offset].v;
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spu_mtfpscr(fpcr);
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}
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static inline void restore_srr0(void)
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{
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unsigned int offset;
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unsigned int srr0;
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/* Restore, Step 14:
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* Restore the SPU SRR0 data from the LSCSA.
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*/
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offset = LSCSA_QW_OFFSET(srr0);
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srr0 = regs_spill[offset].slot[0];
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spu_writech(SPU_WrSRR0, srr0);
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}
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static inline void restore_event_mask(void)
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{
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unsigned int offset;
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unsigned int event_mask;
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/* Restore, Step 15:
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* Restore the SPU_RdEventMsk data from the LSCSA.
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*/
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offset = LSCSA_QW_OFFSET(event_mask);
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event_mask = regs_spill[offset].slot[0];
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spu_writech(SPU_WrEventMask, event_mask);
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}
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static inline void restore_tag_mask(void)
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{
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unsigned int offset;
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unsigned int tag_mask;
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/* Restore, Step 16:
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* Restore the SPU_RdTagMsk data from the LSCSA.
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*/
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offset = LSCSA_QW_OFFSET(tag_mask);
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tag_mask = regs_spill[offset].slot[0];
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spu_writech(MFC_WrTagMask, tag_mask);
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}
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static inline void restore_complete(void)
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{
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extern void exit_fini(void);
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unsigned int *exit_instrs = (unsigned int *)exit_fini;
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unsigned int offset;
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unsigned int stopped_status;
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unsigned int stopped_code;
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/* Restore, Step 18:
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* Issue a stop-and-signal instruction with
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* "good context restore" signal value.
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*
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* Restore, Step 19:
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* There may be additional instructions placed
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* here by the PPE Sequence for SPU Context
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* Restore in order to restore the correct
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* "stopped state".
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*
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* This step is handled here by analyzing the
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* LSCSA.stopped_status and then modifying the
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* exit() function to behave appropriately.
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*/
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offset = LSCSA_QW_OFFSET(stopped_status);
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stopped_status = regs_spill[offset].slot[0];
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stopped_code = regs_spill[offset].slot[1];
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switch (stopped_status) {
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case SPU_STOPPED_STATUS_P_I:
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/* SPU_Status[P,I]=1. Add illegal instruction
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* followed by stop-and-signal instruction after
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* end of restore code.
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*/
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exit_instrs[0] = RESTORE_COMPLETE;
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exit_instrs[1] = ILLEGAL_INSTR;
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exit_instrs[2] = STOP_INSTR | stopped_code;
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break;
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case SPU_STOPPED_STATUS_P_H:
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/* SPU_Status[P,H]=1. Add 'heq $0, $0' followed
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* by stop-and-signal instruction after end of
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* restore code.
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*/
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exit_instrs[0] = RESTORE_COMPLETE;
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exit_instrs[1] = HEQ_INSTR;
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exit_instrs[2] = STOP_INSTR | stopped_code;
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break;
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case SPU_STOPPED_STATUS_S_P:
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/* SPU_Status[S,P]=1. Add nop instruction
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* followed by 'br -4' after end of restore
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* code.
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*/
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exit_instrs[0] = RESTORE_COMPLETE;
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exit_instrs[1] = STOP_INSTR | stopped_code;
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exit_instrs[2] = NOP_INSTR;
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exit_instrs[3] = BR_INSTR;
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break;
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case SPU_STOPPED_STATUS_S_I:
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/* SPU_Status[S,I]=1. Add illegal instruction
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* followed by 'br -4' after end of restore code.
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*/
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exit_instrs[0] = RESTORE_COMPLETE;
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exit_instrs[1] = ILLEGAL_INSTR;
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exit_instrs[2] = NOP_INSTR;
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exit_instrs[3] = BR_INSTR;
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break;
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case SPU_STOPPED_STATUS_I:
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/* SPU_Status[I]=1. Add illegal instruction followed
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* by infinite loop after end of restore sequence.
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*/
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exit_instrs[0] = RESTORE_COMPLETE;
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exit_instrs[1] = ILLEGAL_INSTR;
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exit_instrs[2] = NOP_INSTR;
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exit_instrs[3] = BR_INSTR;
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break;
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case SPU_STOPPED_STATUS_S:
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/* SPU_Status[S]=1. Add two 'nop' instructions. */
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exit_instrs[0] = RESTORE_COMPLETE;
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exit_instrs[1] = NOP_INSTR;
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exit_instrs[2] = NOP_INSTR;
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exit_instrs[3] = BR_INSTR;
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break;
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case SPU_STOPPED_STATUS_H:
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/* SPU_Status[H]=1. Add 'heq $0, $0' instruction
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* after end of restore code.
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*/
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exit_instrs[0] = RESTORE_COMPLETE;
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exit_instrs[1] = HEQ_INSTR;
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exit_instrs[2] = NOP_INSTR;
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exit_instrs[3] = BR_INSTR;
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break;
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case SPU_STOPPED_STATUS_P:
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/* SPU_Status[P]=1. Add stop-and-signal instruction
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* after end of restore code.
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*/
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exit_instrs[0] = RESTORE_COMPLETE;
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exit_instrs[1] = STOP_INSTR | stopped_code;
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break;
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case SPU_STOPPED_STATUS_R:
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/* SPU_Status[I,S,H,P,R]=0. Add infinite loop. */
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exit_instrs[0] = RESTORE_COMPLETE;
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exit_instrs[1] = NOP_INSTR;
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exit_instrs[2] = NOP_INSTR;
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exit_instrs[3] = BR_INSTR;
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break;
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default:
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/* SPU_Status[R]=1. No additional instructions. */
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break;
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}
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spu_sync();
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}
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/**
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* main - entry point for SPU-side context restore.
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*
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* This code deviates from the documented sequence in the
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* following aspects:
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*
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* 1. The EA for LSCSA is passed from PPE in the
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* signal notification channels.
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* 2. The register spill area is pulled by SPU
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* into LS, rather than pushed by PPE.
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* 3. All 128 registers are restored by exit().
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* 4. The exit() function is modified at run
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* time in order to properly restore the
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* SPU_Status register.
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*/
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int main()
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{
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addr64 lscsa_ea;
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lscsa_ea.ui[0] = spu_readch(SPU_RdSigNotify1);
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lscsa_ea.ui[1] = spu_readch(SPU_RdSigNotify2);
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fetch_regs_from_mem(lscsa_ea);
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set_event_mask(); /* Step 1. */
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set_tag_mask(); /* Step 2. */
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build_dma_list(lscsa_ea); /* Step 3. */
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restore_upper_240kb(lscsa_ea); /* Step 4. */
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/* Step 5: done by 'exit'. */
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enqueue_putllc(lscsa_ea); /* Step 7. */
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set_tag_update(); /* Step 8. */
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read_tag_status(); /* Step 9. */
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restore_decr(); /* moved Step 6. */
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read_llar_status(); /* Step 10. */
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write_ppu_mb(); /* Step 11. */
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write_ppuint_mb(); /* Step 12. */
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restore_fpcr(); /* Step 13. */
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restore_srr0(); /* Step 14. */
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restore_event_mask(); /* Step 15. */
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restore_tag_mask(); /* Step 16. */
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/* Step 17. done by 'exit'. */
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restore_complete(); /* Step 18. */
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return 0;
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}
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