835 lines
21 KiB
Plaintext
835 lines
21 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
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#include <dt-bindings/clock/sun6i-rtc.h>
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#include <dt-bindings/clock/sun8i-de2.h>
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#include <dt-bindings/clock/sun8i-tcon-top.h>
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#include <dt-bindings/clock/sun20i-d1-ccu.h>
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#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/reset/sun8i-de2.h>
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#include <dt-bindings/reset/sun20i-d1-ccu.h>
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#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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dcxo: dcxo-clk {
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compatible = "fixed-clock";
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clock-output-names = "dcxo";
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#clock-cells = <0>;
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};
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de: display-engine {
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compatible = "allwinner,sun20i-d1-display-engine";
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allwinner,pipelines = <&mixer0>, <&mixer1>;
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status = "disabled";
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};
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soc {
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compatible = "simple-bus";
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ranges;
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dma-noncoherent;
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#address-cells = <1>;
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#size-cells = <1>;
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pio: pinctrl@2000000 {
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compatible = "allwinner,sun20i-d1-pinctrl";
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reg = <0x2000000 0x800>;
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interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_APB0>,
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<&dcxo>,
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<&rtc CLK_OSC32K>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#gpio-cells = <3>;
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#interrupt-cells = <3>;
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/omit-if-no-ref/
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clk_pg11_pin: clk-pg11-pin {
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pins = "PG11";
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function = "clk";
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};
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/omit-if-no-ref/
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dsi_4lane_pins: dsi-4lane-pins {
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pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
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"PD6", "PD7", "PD8", "PD9";
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drive-strength = <30>;
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function = "dsi";
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};
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/omit-if-no-ref/
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lcd_rgb666_pins: lcd-rgb666-pins {
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pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
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"PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
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"PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
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"PD18", "PD19", "PD20", "PD21";
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function = "lcd0";
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};
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/omit-if-no-ref/
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
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function = "mmc0";
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};
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/omit-if-no-ref/
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mmc1_pins: mmc1-pins {
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pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
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function = "mmc1";
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};
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/omit-if-no-ref/
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mmc2_pins: mmc2-pins {
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pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
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function = "mmc2";
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};
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/omit-if-no-ref/
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rgmii_pe_pins: rgmii-pe-pins {
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pins = "PE0", "PE1", "PE2", "PE3", "PE4",
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"PE5", "PE6", "PE7", "PE8", "PE9",
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"PE11", "PE12", "PE13", "PE14", "PE15";
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function = "emac";
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};
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/omit-if-no-ref/
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rmii_pe_pins: rmii-pe-pins {
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pins = "PE0", "PE1", "PE2", "PE3", "PE4",
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"PE5", "PE6", "PE7", "PE8", "PE9";
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function = "emac";
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};
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/omit-if-no-ref/
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uart1_pg6_pins: uart1-pg6-pins {
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pins = "PG6", "PG7";
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function = "uart1";
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};
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/omit-if-no-ref/
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uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
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pins = "PG8", "PG9";
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function = "uart1";
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};
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/omit-if-no-ref/
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uart3_pb_pins: uart3-pb-pins {
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pins = "PB6", "PB7";
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function = "uart3";
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};
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};
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ccu: clock-controller@2001000 {
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compatible = "allwinner,sun20i-d1-ccu";
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reg = <0x2001000 0x1000>;
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clocks = <&dcxo>,
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<&rtc CLK_OSC32K>,
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<&rtc CLK_IOSC>;
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clock-names = "hosc", "losc", "iosc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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dmic: dmic@2031000 {
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compatible = "allwinner,sun20i-d1-dmic",
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"allwinner,sun50i-h6-dmic";
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reg = <0x2031000 0x400>;
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interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DMIC>,
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<&ccu CLK_DMIC>;
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clock-names = "bus", "mod";
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resets = <&ccu RST_BUS_DMIC>;
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dmas = <&dma 8>;
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dma-names = "rx";
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status = "disabled";
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#sound-dai-cells = <0>;
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};
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i2s1: i2s@2033000 {
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compatible = "allwinner,sun20i-d1-i2s",
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"allwinner,sun50i-r329-i2s";
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reg = <0x2033000 0x1000>;
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interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2S1>,
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<&ccu CLK_I2S1>;
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clock-names = "apb", "mod";
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resets = <&ccu RST_BUS_I2S1>;
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dmas = <&dma 4>, <&dma 4>;
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dma-names = "rx", "tx";
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status = "disabled";
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#sound-dai-cells = <0>;
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};
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i2s2: i2s@2034000 {
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compatible = "allwinner,sun20i-d1-i2s",
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"allwinner,sun50i-r329-i2s";
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reg = <0x2034000 0x1000>;
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interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2S2>,
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<&ccu CLK_I2S2>;
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clock-names = "apb", "mod";
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resets = <&ccu RST_BUS_I2S2>;
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dmas = <&dma 5>, <&dma 5>;
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dma-names = "rx", "tx";
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status = "disabled";
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#sound-dai-cells = <0>;
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};
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timer: timer@2050000 {
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compatible = "allwinner,sun20i-d1-timer",
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"allwinner,sun8i-a23-timer";
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reg = <0x2050000 0xa0>;
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interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dcxo>;
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};
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wdt: watchdog@20500a0 {
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compatible = "allwinner,sun20i-d1-wdt-reset",
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"allwinner,sun20i-d1-wdt";
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reg = <0x20500a0 0x20>;
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interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dcxo>, <&rtc CLK_OSC32K>;
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clock-names = "hosc", "losc";
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status = "reserved";
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};
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uart0: serial@2500000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x2500000 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_UART0>;
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resets = <&ccu RST_BUS_UART0>;
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dmas = <&dma 14>, <&dma 14>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart1: serial@2500400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x2500400 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_UART1>;
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resets = <&ccu RST_BUS_UART1>;
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dmas = <&dma 15>, <&dma 15>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart2: serial@2500800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x2500800 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_UART2>;
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resets = <&ccu RST_BUS_UART2>;
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dmas = <&dma 16>, <&dma 16>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart3: serial@2500c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x2500c00 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_UART3>;
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resets = <&ccu RST_BUS_UART3>;
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dmas = <&dma 17>, <&dma 17>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart4: serial@2501000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x2501000 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_UART4>;
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resets = <&ccu RST_BUS_UART4>;
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dmas = <&dma 18>, <&dma 18>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart5: serial@2501400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x2501400 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_UART5>;
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resets = <&ccu RST_BUS_UART5>;
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dmas = <&dma 19>, <&dma 19>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c0: i2c@2502000 {
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compatible = "allwinner,sun20i-d1-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x2502000 0x400>;
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interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C0>;
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resets = <&ccu RST_BUS_I2C0>;
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dmas = <&dma 43>, <&dma 43>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c1: i2c@2502400 {
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compatible = "allwinner,sun20i-d1-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x2502400 0x400>;
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interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C1>;
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resets = <&ccu RST_BUS_I2C1>;
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dmas = <&dma 44>, <&dma 44>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c2: i2c@2502800 {
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compatible = "allwinner,sun20i-d1-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x2502800 0x400>;
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interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C2>;
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resets = <&ccu RST_BUS_I2C2>;
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dmas = <&dma 45>, <&dma 45>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c3: i2c@2502c00 {
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compatible = "allwinner,sun20i-d1-i2c",
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"allwinner,sun8i-v536-i2c",
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"allwinner,sun6i-a31-i2c";
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reg = <0x2502c00 0x400>;
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interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C3>;
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resets = <&ccu RST_BUS_I2C3>;
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dmas = <&dma 46>, <&dma 46>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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syscon: syscon@3000000 {
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compatible = "allwinner,sun20i-d1-system-control";
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reg = <0x3000000 0x1000>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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dma: dma-controller@3002000 {
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compatible = "allwinner,sun20i-d1-dma";
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reg = <0x3002000 0x1000>;
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interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
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clock-names = "bus", "mbus";
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resets = <&ccu RST_BUS_DMA>;
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dma-channels = <16>;
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dma-requests = <48>;
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#dma-cells = <1>;
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};
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sid: efuse@3006000 {
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compatible = "allwinner,sun20i-d1-sid";
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reg = <0x3006000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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mbus: dram-controller@3102000 {
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compatible = "allwinner,sun20i-d1-mbus";
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reg = <0x3102000 0x1000>,
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<0x3103000 0x1000>;
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reg-names = "mbus", "dram";
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interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_MBUS>,
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<&ccu CLK_DRAM>,
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<&ccu CLK_BUS_DRAM>;
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clock-names = "mbus", "dram", "bus";
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dma-ranges = <0 0x40000000 0x80000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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#interconnect-cells = <1>;
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};
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mmc0: mmc@4020000 {
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compatible = "allwinner,sun20i-d1-mmc";
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reg = <0x4020000 0x1000>;
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interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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cap-sd-highspeed;
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max-frequency = <150000000>;
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no-mmc;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@4021000 {
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compatible = "allwinner,sun20i-d1-mmc";
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reg = <0x4021000 0x1000>;
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interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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cap-sd-highspeed;
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max-frequency = <150000000>;
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no-mmc;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@4022000 {
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compatible = "allwinner,sun20i-d1-emmc",
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"allwinner,sun50i-a100-emmc";
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reg = <0x4022000 0x1000>;
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interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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cap-mmc-highspeed;
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max-frequency = <150000000>;
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mmc-ddr-1_8v;
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mmc-ddr-3_3v;
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no-sd;
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no-sdio;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb_otg: usb@4100000 {
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compatible = "allwinner,sun20i-d1-musb",
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"allwinner,sun8i-a33-musb";
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reg = <0x4100000 0x400>;
|
|
interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mc";
|
|
clocks = <&ccu CLK_BUS_OTG>;
|
|
resets = <&ccu RST_BUS_OTG>;
|
|
extcon = <&usbphy 0>;
|
|
phys = <&usbphy 0>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphy: phy@4100400 {
|
|
compatible = "allwinner,sun20i-d1-usb-phy";
|
|
reg = <0x4100400 0x100>,
|
|
<0x4101800 0x100>,
|
|
<0x4200800 0x100>;
|
|
reg-names = "phy_ctrl",
|
|
"pmu0",
|
|
"pmu1";
|
|
clocks = <&dcxo>,
|
|
<&dcxo>;
|
|
clock-names = "usb0_phy",
|
|
"usb1_phy";
|
|
resets = <&ccu RST_USB_PHY0>,
|
|
<&ccu RST_USB_PHY1>;
|
|
reset-names = "usb0_reset",
|
|
"usb1_reset";
|
|
status = "disabled";
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
ehci0: usb@4101000 {
|
|
compatible = "allwinner,sun20i-d1-ehci",
|
|
"generic-ehci";
|
|
reg = <0x4101000 0x100>;
|
|
interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI0>,
|
|
<&ccu CLK_BUS_EHCI0>,
|
|
<&ccu CLK_USB_OHCI0>;
|
|
resets = <&ccu RST_BUS_OHCI0>,
|
|
<&ccu RST_BUS_EHCI0>;
|
|
phys = <&usbphy 0>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci0: usb@4101400 {
|
|
compatible = "allwinner,sun20i-d1-ohci",
|
|
"generic-ohci";
|
|
reg = <0x4101400 0x100>;
|
|
interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI0>,
|
|
<&ccu CLK_USB_OHCI0>;
|
|
resets = <&ccu RST_BUS_OHCI0>;
|
|
phys = <&usbphy 0>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci1: usb@4200000 {
|
|
compatible = "allwinner,sun20i-d1-ehci",
|
|
"generic-ehci";
|
|
reg = <0x4200000 0x100>;
|
|
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI1>,
|
|
<&ccu CLK_BUS_EHCI1>,
|
|
<&ccu CLK_USB_OHCI1>;
|
|
resets = <&ccu RST_BUS_OHCI1>,
|
|
<&ccu RST_BUS_EHCI1>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci1: usb@4200400 {
|
|
compatible = "allwinner,sun20i-d1-ohci",
|
|
"generic-ohci";
|
|
reg = <0x4200400 0x100>;
|
|
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI1>,
|
|
<&ccu CLK_USB_OHCI1>;
|
|
resets = <&ccu RST_BUS_OHCI1>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
emac: ethernet@4500000 {
|
|
compatible = "allwinner,sun20i-d1-emac",
|
|
"allwinner,sun50i-a64-emac";
|
|
reg = <0x4500000 0x10000>;
|
|
interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
clocks = <&ccu CLK_BUS_EMAC>;
|
|
clock-names = "stmmaceth";
|
|
resets = <&ccu RST_BUS_EMAC>;
|
|
reset-names = "stmmaceth";
|
|
syscon = <&syscon>;
|
|
status = "disabled";
|
|
|
|
mdio: mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
display_clocks: clock-controller@5000000 {
|
|
compatible = "allwinner,sun20i-d1-de2-clk",
|
|
"allwinner,sun50i-h5-de2-clk";
|
|
reg = <0x5000000 0x10000>;
|
|
clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
|
|
clock-names = "bus", "mod";
|
|
resets = <&ccu RST_BUS_DE>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
mixer0: mixer@5100000 {
|
|
compatible = "allwinner,sun20i-d1-de2-mixer-0";
|
|
reg = <0x5100000 0x100000>;
|
|
clocks = <&display_clocks CLK_BUS_MIXER0>,
|
|
<&display_clocks CLK_MIXER0>;
|
|
clock-names = "bus", "mod";
|
|
resets = <&display_clocks RST_MIXER0>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mixer0_out: port@1 {
|
|
reg = <1>;
|
|
|
|
mixer0_out_tcon_top_mixer0: endpoint {
|
|
remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mixer1: mixer@5200000 {
|
|
compatible = "allwinner,sun20i-d1-de2-mixer-1";
|
|
reg = <0x5200000 0x100000>;
|
|
clocks = <&display_clocks CLK_BUS_MIXER1>,
|
|
<&display_clocks CLK_MIXER1>;
|
|
clock-names = "bus", "mod";
|
|
resets = <&display_clocks RST_MIXER1>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mixer1_out: port@1 {
|
|
reg = <1>;
|
|
|
|
mixer1_out_tcon_top_mixer1: endpoint {
|
|
remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dsi: dsi@5450000 {
|
|
compatible = "allwinner,sun20i-d1-mipi-dsi",
|
|
"allwinner,sun50i-a100-mipi-dsi";
|
|
reg = <0x5450000 0x1000>;
|
|
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_MIPI_DSI>,
|
|
<&tcon_top CLK_TCON_TOP_DSI>;
|
|
clock-names = "bus", "mod";
|
|
resets = <&ccu RST_BUS_MIPI_DSI>;
|
|
phys = <&dphy>;
|
|
phy-names = "dphy";
|
|
status = "disabled";
|
|
|
|
port {
|
|
dsi_in_tcon_lcd0: endpoint {
|
|
remote-endpoint = <&tcon_lcd0_out_dsi>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dphy: phy@5451000 {
|
|
compatible = "allwinner,sun20i-d1-mipi-dphy",
|
|
"allwinner,sun50i-a100-mipi-dphy";
|
|
reg = <0x5451000 0x1000>;
|
|
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_MIPI_DSI>,
|
|
<&ccu CLK_MIPI_DSI>;
|
|
clock-names = "bus", "mod";
|
|
resets = <&ccu RST_BUS_MIPI_DSI>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
tcon_top: tcon-top@5460000 {
|
|
compatible = "allwinner,sun20i-d1-tcon-top";
|
|
reg = <0x5460000 0x1000>;
|
|
clocks = <&ccu CLK_BUS_DPSS_TOP>,
|
|
<&ccu CLK_TCON_TV>,
|
|
<&ccu CLK_TVE>,
|
|
<&ccu CLK_TCON_LCD0>;
|
|
clock-names = "bus", "tcon-tv0", "tve0", "dsi";
|
|
clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
|
|
resets = <&ccu RST_BUS_DPSS_TOP>;
|
|
#clock-cells = <1>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_top_mixer0_in: port@0 {
|
|
reg = <0>;
|
|
|
|
tcon_top_mixer0_in_mixer0: endpoint {
|
|
remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
|
|
};
|
|
};
|
|
|
|
tcon_top_mixer0_out: port@1 {
|
|
reg = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
|
|
};
|
|
|
|
tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
|
|
};
|
|
};
|
|
|
|
tcon_top_mixer1_in: port@2 {
|
|
reg = <2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_top_mixer1_in_mixer1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
|
|
};
|
|
};
|
|
|
|
tcon_top_mixer1_out: port@3 {
|
|
reg = <3>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
|
|
};
|
|
|
|
tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
|
|
};
|
|
};
|
|
|
|
tcon_top_hdmi_in: port@4 {
|
|
reg = <4>;
|
|
|
|
tcon_top_hdmi_in_tcon_tv0: endpoint {
|
|
remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
|
|
};
|
|
};
|
|
|
|
tcon_top_hdmi_out: port@5 {
|
|
reg = <5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tcon_lcd0: lcd-controller@5461000 {
|
|
compatible = "allwinner,sun20i-d1-tcon-lcd";
|
|
reg = <0x5461000 0x1000>;
|
|
interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_TCON_LCD0>,
|
|
<&ccu CLK_TCON_LCD0>;
|
|
clock-names = "ahb", "tcon-ch0";
|
|
clock-output-names = "tcon-pixel-clock";
|
|
resets = <&ccu RST_BUS_TCON_LCD0>,
|
|
<&ccu RST_BUS_LVDS0>;
|
|
reset-names = "lcd", "lvds";
|
|
#clock-cells = <0>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_lcd0_in: port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
|
|
};
|
|
|
|
tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
|
|
};
|
|
};
|
|
|
|
tcon_lcd0_out: port@1 {
|
|
reg = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_lcd0_out_dsi: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&dsi_in_tcon_lcd0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tcon_tv0: lcd-controller@5470000 {
|
|
compatible = "allwinner,sun20i-d1-tcon-tv";
|
|
reg = <0x5470000 0x1000>;
|
|
interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_TCON_TV>,
|
|
<&tcon_top CLK_TCON_TOP_TV0>;
|
|
clock-names = "ahb", "tcon-ch1";
|
|
resets = <&ccu RST_BUS_TCON_TV>;
|
|
reset-names = "lcd";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_tv0_in: port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
|
|
};
|
|
|
|
tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
|
|
};
|
|
};
|
|
|
|
tcon_tv0_out: port@1 {
|
|
reg = <1>;
|
|
|
|
tcon_tv0_out_tcon_top_hdmi: endpoint {
|
|
remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ppu: power-controller@7001000 {
|
|
compatible = "allwinner,sun20i-d1-ppu";
|
|
reg = <0x7001000 0x1000>;
|
|
clocks = <&r_ccu CLK_BUS_R_PPU>;
|
|
resets = <&r_ccu RST_BUS_R_PPU>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
r_ccu: clock-controller@7010000 {
|
|
compatible = "allwinner,sun20i-d1-r-ccu";
|
|
reg = <0x7010000 0x400>;
|
|
clocks = <&dcxo>,
|
|
<&rtc CLK_OSC32K>,
|
|
<&rtc CLK_IOSC>,
|
|
<&ccu CLK_PLL_PERIPH0_DIV3>;
|
|
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
rtc: rtc@7090000 {
|
|
compatible = "allwinner,sun20i-d1-rtc",
|
|
"allwinner,sun50i-r329-rtc";
|
|
reg = <0x7090000 0x400>;
|
|
interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_BUS_R_RTC>,
|
|
<&dcxo>,
|
|
<&r_ccu CLK_R_AHB>;
|
|
clock-names = "bus", "hosc", "ahb";
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
};
|