206 lines
2.9 KiB
Plaintext
206 lines
2.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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/dts-v1/;
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#include "mpfs.dtsi"
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#include "mpfs-icicle-kit-fabric.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/* Clock frequency (in Hz) of the rtcclk */
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#define RTCCLK_FREQ 1000000
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/ {
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model = "Microchip PolarFire-SoC Icicle Kit";
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compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
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"microchip,mpfs";
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aliases {
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ethernet0 = &mac1;
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serial0 = &mmuart0;
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serial1 = &mmuart1;
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serial2 = &mmuart2;
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serial3 = &mmuart3;
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serial4 = &mmuart4;
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};
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chosen {
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stdout-path = "serial1:115200n8";
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};
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cpus {
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timebase-frequency = <RTCCLK_FREQ>;
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};
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leds {
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compatible = "gpio-leds";
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led-1 {
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gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_RED>;
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label = "led1";
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};
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led-2 {
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gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_RED>;
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label = "led2";
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};
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led-3 {
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gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_AMBER>;
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label = "led3";
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};
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led-4 {
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gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_AMBER>;
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label = "led4";
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};
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};
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ddrc_cache_lo: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x40000000>;
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status = "okay";
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};
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ddrc_cache_hi: memory@1040000000 {
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device_type = "memory";
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reg = <0x10 0x40000000 0x0 0x40000000>;
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status = "okay";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hss_payload: region@BFC00000 {
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reg = <0x0 0xBFC00000 0x0 0x400000>;
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no-map;
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};
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};
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};
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&core_pwm0 {
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status = "okay";
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};
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&gpio2 {
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interrupts = <53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>;
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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};
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&mac0 {
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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status = "okay";
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};
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&mac1 {
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phy-mode = "sgmii";
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phy-handle = <&phy1>;
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status = "okay";
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phy1: ethernet-phy@9 {
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reg = <9>;
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};
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phy0: ethernet-phy@8 {
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reg = <8>;
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};
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};
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&mbox {
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status = "okay";
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};
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&mmc {
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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&mmuart1 {
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status = "okay";
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};
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&mmuart2 {
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status = "okay";
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};
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&mmuart3 {
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status = "okay";
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};
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&mmuart4 {
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status = "okay";
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};
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&pcie {
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status = "okay";
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};
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&qspi {
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status = "okay";
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};
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&refclk {
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clock-frequency = <125000000>;
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};
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&refclk_ccc {
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clock-frequency = <50000000>;
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};
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&rtc {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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};
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&spi1 {
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status = "okay";
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};
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&syscontroller {
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status = "okay";
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};
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&usb {
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status = "okay";
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dr_mode = "host";
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};
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