678 lines
19 KiB
ArmAsm
678 lines
19 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* S390 low-level entry points.
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*
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* Copyright IBM Corp. 1999, 2012
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
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* Hartmut Penner (hp@de.ibm.com),
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* Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/asm-extable.h>
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#include <asm/alternative-asm.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/dwarf.h>
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#include <asm/errno.h>
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#include <asm/ptrace.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/unistd.h>
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#include <asm/page.h>
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#include <asm/sigp.h>
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#include <asm/irq.h>
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#include <asm/vx-insn.h>
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#include <asm/setup.h>
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#include <asm/nmi.h>
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#include <asm/export.h>
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#include <asm/nospec-insn.h>
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STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
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STACK_SIZE = 1 << STACK_SHIFT
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STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
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_LPP_OFFSET = __LC_LPP
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.macro STBEAR address
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ALTERNATIVE "nop", ".insn s,0xb2010000,\address", 193
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.endm
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.macro LBEAR address
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ALTERNATIVE "nop", ".insn s,0xb2000000,\address", 193
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.endm
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.macro LPSWEY address,lpswe
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ALTERNATIVE "b \lpswe; nopr", ".insn siy,0xeb0000000071,\address,0", 193
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.endm
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.macro MBEAR reg
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ALTERNATIVE "brcl 0,0", __stringify(mvc __PT_LAST_BREAK(8,\reg),__LC_LAST_BREAK), 193
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.endm
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.macro CHECK_STACK savearea
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#ifdef CONFIG_CHECK_STACK
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tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
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lghi %r14,\savearea
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jz stack_overflow
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#endif
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.endm
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.macro CHECK_VMAP_STACK savearea,oklabel
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#ifdef CONFIG_VMAP_STACK
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lgr %r14,%r15
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nill %r14,0x10000 - STACK_SIZE
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oill %r14,STACK_INIT
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clg %r14,__LC_KERNEL_STACK
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je \oklabel
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clg %r14,__LC_ASYNC_STACK
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je \oklabel
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clg %r14,__LC_MCCK_STACK
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je \oklabel
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clg %r14,__LC_NODAT_STACK
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je \oklabel
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clg %r14,__LC_RESTART_STACK
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je \oklabel
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lghi %r14,\savearea
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j stack_overflow
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#else
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j \oklabel
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#endif
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.endm
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/*
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* The TSTMSK macro generates a test-under-mask instruction by
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* calculating the memory offset for the specified mask value.
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* Mask value can be any constant. The macro shifts the mask
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* value to calculate the memory offset for the test-under-mask
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* instruction.
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*/
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.macro TSTMSK addr, mask, size=8, bytepos=0
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.if (\bytepos < \size) && (\mask >> 8)
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.if (\mask & 0xff)
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.error "Mask exceeds byte boundary"
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.endif
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TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
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.exitm
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.endif
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.ifeq \mask
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.error "Mask must not be zero"
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.endif
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off = \size - \bytepos - 1
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tm off+\addr, \mask
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.endm
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.macro BPOFF
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ALTERNATIVE "nop", ".insn rrf,0xb2e80000,0,0,12,0", 82
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.endm
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.macro BPON
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ALTERNATIVE "nop", ".insn rrf,0xb2e80000,0,0,13,0", 82
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.endm
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.macro BPENTER tif_ptr,tif_mask
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ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .insn rrf,0xb2e80000,0,0,13,0", \
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"j .+12; nop; nop", 82
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.endm
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.macro BPEXIT tif_ptr,tif_mask
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TSTMSK \tif_ptr,\tif_mask
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ALTERNATIVE "jz .+8; .insn rrf,0xb2e80000,0,0,12,0", \
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"jnz .+8; .insn rrf,0xb2e80000,0,0,13,0", 82
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.endm
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#if IS_ENABLED(CONFIG_KVM)
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/*
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* The OUTSIDE macro jumps to the provided label in case the value
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* in the provided register is outside of the provided range. The
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* macro is useful for checking whether a PSW stored in a register
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* pair points inside or outside of a block of instructions.
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* @reg: register to check
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* @start: start of the range
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* @end: end of the range
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* @outside_label: jump here if @reg is outside of [@start..@end)
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*/
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.macro OUTSIDE reg,start,end,outside_label
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lgr %r14,\reg
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larl %r13,\start
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slgr %r14,%r13
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clgfrl %r14,.Lrange_size\@
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jhe \outside_label
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.section .rodata, "a"
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.align 4
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.Lrange_size\@:
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.long \end - \start
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.previous
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.endm
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.macro SIEEXIT
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lg %r9,__SF_SIE_CONTROL(%r15) # get control block pointer
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ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
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lctlg %c1,%c1,__LC_KERNEL_ASCE # load primary asce
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larl %r9,sie_exit # skip forward to sie_exit
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.endm
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#endif
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GEN_BR_THUNK %r14
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.section .kprobes.text, "ax"
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.Ldummy:
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/*
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* This nop exists only in order to avoid that __bpon starts at
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* the beginning of the kprobes text section. In that case we would
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* have several symbols at the same address. E.g. objdump would take
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* an arbitrary symbol name when disassembling this code.
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* With the added nop in between the __bpon symbol is unique
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* again.
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*/
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nop 0
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ENTRY(__bpon)
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.globl __bpon
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BPON
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BR_EX %r14
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ENDPROC(__bpon)
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/*
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* Scheduler resume function, called by switch_to
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* gpr2 = (task_struct *) prev
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* gpr3 = (task_struct *) next
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* Returns:
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* gpr2 = prev
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*/
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ENTRY(__switch_to)
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stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task
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lghi %r4,__TASK_stack
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lghi %r1,__TASK_thread
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llill %r5,STACK_INIT
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stg %r15,__THREAD_ksp(%r1,%r2) # store kernel stack of prev
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lg %r15,0(%r4,%r3) # start of kernel stack of next
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agr %r15,%r5 # end of kernel stack of next
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stg %r3,__LC_CURRENT # store task struct of next
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stg %r15,__LC_KERNEL_STACK # store end of kernel stack
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lg %r15,__THREAD_ksp(%r1,%r3) # load kernel stack of next
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aghi %r3,__TASK_pid
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mvc __LC_CURRENT_PID(4,%r0),0(%r3) # store pid of next
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lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
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ALTERNATIVE "nop", "lpp _LPP_OFFSET", 40
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BR_EX %r14
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ENDPROC(__switch_to)
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#if IS_ENABLED(CONFIG_KVM)
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/*
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* __sie64a calling convention:
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* %r2 pointer to sie control block phys
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* %r3 pointer to sie control block virt
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* %r4 guest register save area
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*/
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ENTRY(__sie64a)
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stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers
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lg %r12,__LC_CURRENT
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stg %r2,__SF_SIE_CONTROL_PHYS(%r15) # save sie block physical..
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stg %r3,__SF_SIE_CONTROL(%r15) # ...and virtual addresses
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stg %r4,__SF_SIE_SAVEAREA(%r15) # save guest register save area
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xc __SF_SIE_REASON(8,%r15),__SF_SIE_REASON(%r15) # reason code = 0
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mvc __SF_SIE_FLAGS(8,%r15),__TI_flags(%r12) # copy thread flags
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lmg %r0,%r13,0(%r4) # load guest gprs 0-13
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lg %r14,__LC_GMAP # get gmap pointer
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ltgr %r14,%r14
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jz .Lsie_gmap
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lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
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.Lsie_gmap:
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lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
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oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now
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tm __SIE_PROG20+3(%r14),3 # last exit...
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jnz .Lsie_skip
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TSTMSK __LC_CPU_FLAGS,_CIF_FPU
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jo .Lsie_skip # exit if fp/vx regs changed
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lg %r14,__SF_SIE_CONTROL_PHYS(%r15) # get sie block phys addr
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BPEXIT __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
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.Lsie_entry:
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sie 0(%r14)
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# Let the next instruction be NOP to avoid triggering a machine check
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# and handling it in a guest as result of the instruction execution.
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nopr 7
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.Lsie_leave:
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BPOFF
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BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
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.Lsie_skip:
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lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
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ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
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lctlg %c1,%c1,__LC_KERNEL_ASCE # load primary asce
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.Lsie_done:
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# some program checks are suppressing. C code (e.g. do_protection_exception)
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# will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
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# are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
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# Other instructions between __sie64a and .Lsie_done should not cause program
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# interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
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.Lrewind_pad6:
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nopr 7
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.Lrewind_pad4:
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nopr 7
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.Lrewind_pad2:
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nopr 7
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.globl sie_exit
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sie_exit:
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lg %r14,__SF_SIE_SAVEAREA(%r15) # load guest register save area
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stmg %r0,%r13,0(%r14) # save guest gprs 0-13
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xgr %r0,%r0 # clear guest registers to
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xgr %r1,%r1 # prevent speculative use
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xgr %r3,%r3
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xgr %r4,%r4
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xgr %r5,%r5
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lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
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lg %r2,__SF_SIE_REASON(%r15) # return exit reason code
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BR_EX %r14
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.Lsie_fault:
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lghi %r14,-EFAULT
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stg %r14,__SF_SIE_REASON(%r15) # set exit reason code
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j sie_exit
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EX_TABLE(.Lrewind_pad6,.Lsie_fault)
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EX_TABLE(.Lrewind_pad4,.Lsie_fault)
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EX_TABLE(.Lrewind_pad2,.Lsie_fault)
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EX_TABLE(sie_exit,.Lsie_fault)
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ENDPROC(__sie64a)
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EXPORT_SYMBOL(__sie64a)
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EXPORT_SYMBOL(sie_exit)
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#endif
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/*
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* SVC interrupt handler routine. System calls are synchronous events and
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* are entered with interrupts disabled.
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*/
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ENTRY(system_call)
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stpt __LC_SYS_ENTER_TIMER
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stmg %r8,%r15,__LC_SAVE_AREA_SYNC
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BPOFF
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lghi %r14,0
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.Lsysc_per:
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STBEAR __LC_LAST_BREAK
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lctlg %c1,%c1,__LC_KERNEL_ASCE
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lg %r12,__LC_CURRENT
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lg %r15,__LC_KERNEL_STACK
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xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
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stmg %r0,%r7,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
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BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
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# clear user controlled register to prevent speculative use
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xgr %r0,%r0
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xgr %r1,%r1
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xgr %r4,%r4
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xgr %r5,%r5
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xgr %r6,%r6
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xgr %r7,%r7
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xgr %r8,%r8
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xgr %r9,%r9
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xgr %r10,%r10
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xgr %r11,%r11
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la %r2,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
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mvc __PT_R8(64,%r2),__LC_SAVE_AREA_SYNC
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MBEAR %r2
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lgr %r3,%r14
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brasl %r14,__do_syscall
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lctlg %c1,%c1,__LC_USER_ASCE
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mvc __LC_RETURN_PSW(16),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
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BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
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LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
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lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
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stpt __LC_EXIT_TIMER
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LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
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ENDPROC(system_call)
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#
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# a new process exits the kernel with ret_from_fork
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#
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ENTRY(ret_from_fork)
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lgr %r3,%r11
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brasl %r14,__ret_from_fork
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lctlg %c1,%c1,__LC_USER_ASCE
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mvc __LC_RETURN_PSW(16),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
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BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
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LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
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lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
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stpt __LC_EXIT_TIMER
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LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
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ENDPROC(ret_from_fork)
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/*
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* Program check handler routine
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*/
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ENTRY(pgm_check_handler)
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stpt __LC_SYS_ENTER_TIMER
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BPOFF
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stmg %r8,%r15,__LC_SAVE_AREA_SYNC
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lg %r12,__LC_CURRENT
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lghi %r10,0
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lmg %r8,%r9,__LC_PGM_OLD_PSW
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tmhh %r8,0x0001 # coming from user space?
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jno .Lpgm_skip_asce
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lctlg %c1,%c1,__LC_KERNEL_ASCE
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j 3f # -> fault in user space
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.Lpgm_skip_asce:
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#if IS_ENABLED(CONFIG_KVM)
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# cleanup critical section for program checks in __sie64a
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OUTSIDE %r9,.Lsie_gmap,.Lsie_done,1f
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SIEEXIT
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lghi %r10,_PIF_GUEST_FAULT
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#endif
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1: tmhh %r8,0x4000 # PER bit set in old PSW ?
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jnz 2f # -> enabled, can't be a double fault
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tm __LC_PGM_ILC+3,0x80 # check for per exception
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jnz .Lpgm_svcper # -> single stepped svc
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2: CHECK_STACK __LC_SAVE_AREA_SYNC
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aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
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# CHECK_VMAP_STACK branches to stack_overflow or 4f
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CHECK_VMAP_STACK __LC_SAVE_AREA_SYNC,4f
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3: BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
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lg %r15,__LC_KERNEL_STACK
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4: la %r11,STACK_FRAME_OVERHEAD(%r15)
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stg %r10,__PT_FLAGS(%r11)
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xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
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stmg %r0,%r7,__PT_R0(%r11)
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mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
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mvc __PT_LAST_BREAK(8,%r11),__LC_PGM_LAST_BREAK
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stmg %r8,%r9,__PT_PSW(%r11)
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# clear user controlled registers to prevent speculative use
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xgr %r0,%r0
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xgr %r1,%r1
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xgr %r3,%r3
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xgr %r4,%r4
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xgr %r5,%r5
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xgr %r6,%r6
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xgr %r7,%r7
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lgr %r2,%r11
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brasl %r14,__do_pgm_check
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tmhh %r8,0x0001 # returning to user space?
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jno .Lpgm_exit_kernel
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lctlg %c1,%c1,__LC_USER_ASCE
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BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
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stpt __LC_EXIT_TIMER
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.Lpgm_exit_kernel:
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mvc __LC_RETURN_PSW(16),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
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LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
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lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
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LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
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#
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# single stepped system call
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#
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.Lpgm_svcper:
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mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
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larl %r14,.Lsysc_per
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stg %r14,__LC_RETURN_PSW+8
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lghi %r14,1
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LBEAR __LC_PGM_LAST_BREAK
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LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE # branch to .Lsysc_per
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ENDPROC(pgm_check_handler)
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/*
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* Interrupt handler macro used for external and IO interrupts.
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*/
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.macro INT_HANDLER name,lc_old_psw,handler
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ENTRY(\name)
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stckf __LC_INT_CLOCK
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stpt __LC_SYS_ENTER_TIMER
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STBEAR __LC_LAST_BREAK
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BPOFF
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stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
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lg %r12,__LC_CURRENT
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lmg %r8,%r9,\lc_old_psw
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tmhh %r8,0x0001 # interrupting from user ?
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jnz 1f
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#if IS_ENABLED(CONFIG_KVM)
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OUTSIDE %r9,.Lsie_gmap,.Lsie_done,0f
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BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
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SIEEXIT
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#endif
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0: CHECK_STACK __LC_SAVE_AREA_ASYNC
|
|
aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
|
|
j 2f
|
|
1: BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
|
|
lctlg %c1,%c1,__LC_KERNEL_ASCE
|
|
lg %r15,__LC_KERNEL_STACK
|
|
2: xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
|
|
la %r11,STACK_FRAME_OVERHEAD(%r15)
|
|
stmg %r0,%r7,__PT_R0(%r11)
|
|
# clear user controlled registers to prevent speculative use
|
|
xgr %r0,%r0
|
|
xgr %r1,%r1
|
|
xgr %r3,%r3
|
|
xgr %r4,%r4
|
|
xgr %r5,%r5
|
|
xgr %r6,%r6
|
|
xgr %r7,%r7
|
|
xgr %r10,%r10
|
|
xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
|
|
mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
|
|
MBEAR %r11
|
|
stmg %r8,%r9,__PT_PSW(%r11)
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
|
brasl %r14,\handler
|
|
mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
|
|
tmhh %r8,0x0001 # returning to user ?
|
|
jno 2f
|
|
lctlg %c1,%c1,__LC_USER_ASCE
|
|
BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
|
|
stpt __LC_EXIT_TIMER
|
|
2: LBEAR __PT_LAST_BREAK(%r11)
|
|
lmg %r0,%r15,__PT_R0(%r11)
|
|
LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE
|
|
ENDPROC(\name)
|
|
.endm
|
|
|
|
INT_HANDLER ext_int_handler,__LC_EXT_OLD_PSW,do_ext_irq
|
|
INT_HANDLER io_int_handler,__LC_IO_OLD_PSW,do_io_irq
|
|
|
|
/*
|
|
* Load idle PSW.
|
|
*/
|
|
ENTRY(psw_idle)
|
|
stg %r14,(__SF_GPRS+8*8)(%r15)
|
|
stg %r3,__SF_EMPTY(%r15)
|
|
larl %r1,psw_idle_exit
|
|
stg %r1,__SF_EMPTY+8(%r15)
|
|
larl %r1,smp_cpu_mtid
|
|
llgf %r1,0(%r1)
|
|
ltgr %r1,%r1
|
|
jz .Lpsw_idle_stcctm
|
|
.insn rsy,0xeb0000000017,%r1,5,__MT_CYCLES_ENTER(%r2)
|
|
.Lpsw_idle_stcctm:
|
|
oi __LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
|
|
BPON
|
|
stckf __CLOCK_IDLE_ENTER(%r2)
|
|
stpt __TIMER_IDLE_ENTER(%r2)
|
|
lpswe __SF_EMPTY(%r15)
|
|
.globl psw_idle_exit
|
|
psw_idle_exit:
|
|
BR_EX %r14
|
|
ENDPROC(psw_idle)
|
|
|
|
/*
|
|
* Machine check handler routines
|
|
*/
|
|
ENTRY(mcck_int_handler)
|
|
stckf __LC_MCCK_CLOCK
|
|
BPOFF
|
|
la %r1,4095 # validate r1
|
|
spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # validate cpu timer
|
|
LBEAR __LC_LAST_BREAK_SAVE_AREA-4095(%r1) # validate bear
|
|
lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs
|
|
lg %r12,__LC_CURRENT
|
|
lmg %r8,%r9,__LC_MCK_OLD_PSW
|
|
TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
|
|
jo .Lmcck_panic # yes -> rest of mcck code invalid
|
|
TSTMSK __LC_MCCK_CODE,MCCK_CODE_CR_VALID
|
|
jno .Lmcck_panic # control registers invalid -> panic
|
|
la %r14,4095
|
|
lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs
|
|
ptlb
|
|
lghi %r14,__LC_CPU_TIMER_SAVE_AREA
|
|
mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
|
|
TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
|
|
jo 3f
|
|
la %r14,__LC_SYS_ENTER_TIMER
|
|
clc 0(8,%r14),__LC_EXIT_TIMER
|
|
jl 1f
|
|
la %r14,__LC_EXIT_TIMER
|
|
1: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
|
|
jl 2f
|
|
la %r14,__LC_LAST_UPDATE_TIMER
|
|
2: spt 0(%r14)
|
|
mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
|
|
3: TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID
|
|
jno .Lmcck_panic
|
|
tmhh %r8,0x0001 # interrupting from user ?
|
|
jnz .Lmcck_user
|
|
TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID
|
|
jno .Lmcck_panic
|
|
#if IS_ENABLED(CONFIG_KVM)
|
|
OUTSIDE %r9,.Lsie_gmap,.Lsie_done,.Lmcck_stack
|
|
OUTSIDE %r9,.Lsie_entry,.Lsie_leave,4f
|
|
oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
|
|
4: BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
|
|
SIEEXIT
|
|
j .Lmcck_stack
|
|
#endif
|
|
.Lmcck_user:
|
|
BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
|
|
.Lmcck_stack:
|
|
lg %r15,__LC_MCCK_STACK
|
|
la %r11,STACK_FRAME_OVERHEAD(%r15)
|
|
stctg %c1,%c1,__PT_CR1(%r11)
|
|
lctlg %c1,%c1,__LC_KERNEL_ASCE
|
|
xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
|
|
lghi %r14,__LC_GPREGS_SAVE_AREA+64
|
|
stmg %r0,%r7,__PT_R0(%r11)
|
|
# clear user controlled registers to prevent speculative use
|
|
xgr %r0,%r0
|
|
xgr %r1,%r1
|
|
xgr %r3,%r3
|
|
xgr %r4,%r4
|
|
xgr %r5,%r5
|
|
xgr %r6,%r6
|
|
xgr %r7,%r7
|
|
xgr %r10,%r10
|
|
mvc __PT_R8(64,%r11),0(%r14)
|
|
stmg %r8,%r9,__PT_PSW(%r11)
|
|
xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
|
|
xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
|
brasl %r14,s390_do_machine_check
|
|
lctlg %c1,%c1,__PT_CR1(%r11)
|
|
lmg %r0,%r10,__PT_R0(%r11)
|
|
mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
|
|
tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
|
|
jno 0f
|
|
BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
|
|
stpt __LC_EXIT_TIMER
|
|
0: ALTERNATIVE "nop", __stringify(lghi %r12,__LC_LAST_BREAK_SAVE_AREA),193
|
|
LBEAR 0(%r12)
|
|
lmg %r11,%r15,__PT_R11(%r11)
|
|
LPSWEY __LC_RETURN_MCCK_PSW,__LC_RETURN_MCCK_LPSWE
|
|
|
|
.Lmcck_panic:
|
|
/*
|
|
* Iterate over all possible CPU addresses in the range 0..0xffff
|
|
* and stop each CPU using signal processor. Use compare and swap
|
|
* to allow just one CPU-stopper and prevent concurrent CPUs from
|
|
* stopping each other while leaving the others running.
|
|
*/
|
|
lhi %r5,0
|
|
lhi %r6,1
|
|
larl %r7,.Lstop_lock
|
|
cs %r5,%r6,0(%r7) # single CPU-stopper only
|
|
jnz 4f
|
|
larl %r7,.Lthis_cpu
|
|
stap 0(%r7) # this CPU address
|
|
lh %r4,0(%r7)
|
|
nilh %r4,0
|
|
lhi %r0,1
|
|
sll %r0,16 # CPU counter
|
|
lhi %r3,0 # next CPU address
|
|
0: cr %r3,%r4
|
|
je 2f
|
|
1: sigp %r1,%r3,SIGP_STOP # stop next CPU
|
|
brc SIGP_CC_BUSY,1b
|
|
2: ahi %r3,1
|
|
brct %r0,0b
|
|
3: sigp %r1,%r4,SIGP_STOP # stop this CPU
|
|
brc SIGP_CC_BUSY,3b
|
|
4: j 4b
|
|
ENDPROC(mcck_int_handler)
|
|
|
|
ENTRY(restart_int_handler)
|
|
ALTERNATIVE "nop", "lpp _LPP_OFFSET", 40
|
|
stg %r15,__LC_SAVE_AREA_RESTART
|
|
TSTMSK __LC_RESTART_FLAGS,RESTART_FLAG_CTLREGS,4
|
|
jz 0f
|
|
la %r15,4095
|
|
lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r15)
|
|
0: larl %r15,.Lstosm_tmp
|
|
stosm 0(%r15),0x04 # turn dat on, keep irqs off
|
|
lg %r15,__LC_RESTART_STACK
|
|
xc STACK_FRAME_OVERHEAD(__PT_SIZE,%r15),STACK_FRAME_OVERHEAD(%r15)
|
|
stmg %r0,%r14,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
|
|
mvc STACK_FRAME_OVERHEAD+__PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
|
|
mvc STACK_FRAME_OVERHEAD+__PT_PSW(16,%r15),__LC_RST_OLD_PSW
|
|
xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
|
|
lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
|
|
lg %r2,__LC_RESTART_DATA
|
|
lgf %r3,__LC_RESTART_SOURCE
|
|
ltgr %r3,%r3 # test source cpu address
|
|
jm 1f # negative -> skip source stop
|
|
0: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu
|
|
brc 10,0b # wait for status stored
|
|
1: basr %r14,%r1 # call function
|
|
stap __SF_EMPTY(%r15) # store cpu address
|
|
llgh %r3,__SF_EMPTY(%r15)
|
|
2: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu
|
|
brc 2,2b
|
|
3: j 3b
|
|
ENDPROC(restart_int_handler)
|
|
|
|
.section .kprobes.text, "ax"
|
|
|
|
#if defined(CONFIG_CHECK_STACK) || defined(CONFIG_VMAP_STACK)
|
|
/*
|
|
* The synchronous or the asynchronous stack overflowed. We are dead.
|
|
* No need to properly save the registers, we are going to panic anyway.
|
|
* Setup a pt_regs so that show_trace can provide a good call trace.
|
|
*/
|
|
ENTRY(stack_overflow)
|
|
lg %r15,__LC_NODAT_STACK # change to panic stack
|
|
la %r11,STACK_FRAME_OVERHEAD(%r15)
|
|
stmg %r0,%r7,__PT_R0(%r11)
|
|
stmg %r8,%r9,__PT_PSW(%r11)
|
|
mvc __PT_R8(64,%r11),0(%r14)
|
|
stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
|
|
xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
|
jg kernel_stack_overflow
|
|
ENDPROC(stack_overflow)
|
|
#endif
|
|
|
|
.section .data, "aw"
|
|
.align 4
|
|
.Lstop_lock: .long 0
|
|
.Lthis_cpu: .short 0
|
|
.Lstosm_tmp: .byte 0
|
|
.section .rodata, "a"
|
|
#define SYSCALL(esame,emu) .quad __s390x_ ## esame
|
|
.globl sys_call_table
|
|
sys_call_table:
|
|
#include "asm/syscall_table.h"
|
|
#undef SYSCALL
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
|
|
#define SYSCALL(esame,emu) .quad __s390_ ## emu
|
|
.globl sys_call_table_emu
|
|
sys_call_table_emu:
|
|
#include "asm/syscall_table.h"
|
|
#undef SYSCALL
|
|
#endif
|