473 lines
14 KiB
C
473 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* psycho_common.c: Code common to PSYCHO and derivative PCI controllers.
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*
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* Copyright (C) 2008 David S. Miller <davem@davemloft.net>
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/numa.h>
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#include <asm/upa.h>
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#include "pci_impl.h"
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#include "iommu_common.h"
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#include "psycho_common.h"
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#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002ULL
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#define PSYCHO_STCERR_WRITE 0x0000000000000002ULL
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#define PSYCHO_STCERR_READ 0x0000000000000001ULL
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#define PSYCHO_STCTAG_PPN 0x0fffffff00000000ULL
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#define PSYCHO_STCTAG_VPN 0x00000000ffffe000ULL
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#define PSYCHO_STCTAG_VALID 0x0000000000000002ULL
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#define PSYCHO_STCTAG_WRITE 0x0000000000000001ULL
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#define PSYCHO_STCLINE_LINDX 0x0000000001e00000ULL
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#define PSYCHO_STCLINE_SPTR 0x00000000001f8000ULL
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#define PSYCHO_STCLINE_LADDR 0x0000000000007f00ULL
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#define PSYCHO_STCLINE_EPTR 0x00000000000000fcULL
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#define PSYCHO_STCLINE_VALID 0x0000000000000002ULL
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#define PSYCHO_STCLINE_FOFN 0x0000000000000001ULL
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static DEFINE_SPINLOCK(stc_buf_lock);
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static unsigned long stc_error_buf[128];
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static unsigned long stc_tag_buf[16];
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static unsigned long stc_line_buf[16];
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static void psycho_check_stc_error(struct pci_pbm_info *pbm)
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{
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unsigned long err_base, tag_base, line_base;
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struct strbuf *strbuf = &pbm->stc;
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u64 control;
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int i;
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if (!strbuf->strbuf_control)
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return;
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err_base = strbuf->strbuf_err_stat;
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tag_base = strbuf->strbuf_tag_diag;
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line_base = strbuf->strbuf_line_diag;
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spin_lock(&stc_buf_lock);
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/* This is __REALLY__ dangerous. When we put the streaming
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* buffer into diagnostic mode to probe it's tags and error
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* status, we _must_ clear all of the line tag valid bits
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* before re-enabling the streaming buffer. If any dirty data
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* lives in the STC when we do this, we will end up
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* invalidating it before it has a chance to reach main
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* memory.
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*/
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control = upa_readq(strbuf->strbuf_control);
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upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control);
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for (i = 0; i < 128; i++) {
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u64 val;
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val = upa_readq(err_base + (i * 8UL));
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upa_writeq(0UL, err_base + (i * 8UL));
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stc_error_buf[i] = val;
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}
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for (i = 0; i < 16; i++) {
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stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
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stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
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upa_writeq(0UL, tag_base + (i * 8UL));
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upa_writeq(0UL, line_base + (i * 8UL));
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}
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/* OK, state is logged, exit diagnostic mode. */
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upa_writeq(control, strbuf->strbuf_control);
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for (i = 0; i < 16; i++) {
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int j, saw_error, first, last;
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saw_error = 0;
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first = i * 8;
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last = first + 8;
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for (j = first; j < last; j++) {
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u64 errval = stc_error_buf[j];
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if (errval != 0) {
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saw_error++;
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printk(KERN_ERR "%s: STC_ERR(%d)[wr(%d)"
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"rd(%d)]\n",
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pbm->name,
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j,
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(errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
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(errval & PSYCHO_STCERR_READ) ? 1 : 0);
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}
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}
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if (saw_error != 0) {
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u64 tagval = stc_tag_buf[i];
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u64 lineval = stc_line_buf[i];
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printk(KERN_ERR "%s: STC_TAG(%d)[PA(%016llx)VA(%08llx)"
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"V(%d)W(%d)]\n",
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pbm->name,
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i,
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((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
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(tagval & PSYCHO_STCTAG_VPN),
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((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
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((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
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printk(KERN_ERR "%s: STC_LINE(%d)[LIDX(%llx)SP(%llx)"
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"LADDR(%llx)EP(%llx)V(%d)FOFN(%d)]\n",
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pbm->name,
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i,
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((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
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((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
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((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
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((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
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((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
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((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
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}
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}
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spin_unlock(&stc_buf_lock);
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}
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#define PSYCHO_IOMMU_TAG 0xa580UL
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#define PSYCHO_IOMMU_DATA 0xa600UL
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static void psycho_record_iommu_tags_and_data(struct pci_pbm_info *pbm,
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u64 *tag, u64 *data)
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{
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int i;
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for (i = 0; i < 16; i++) {
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unsigned long base = pbm->controller_regs;
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unsigned long off = i * 8UL;
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tag[i] = upa_readq(base + PSYCHO_IOMMU_TAG+off);
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data[i] = upa_readq(base + PSYCHO_IOMMU_DATA+off);
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/* Now clear out the entry. */
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upa_writeq(0, base + PSYCHO_IOMMU_TAG + off);
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upa_writeq(0, base + PSYCHO_IOMMU_DATA + off);
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}
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}
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#define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
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#define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
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#define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
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#define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
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#define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
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#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffULL
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#define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
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#define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
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#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffULL
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static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm,
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u64 *tag, u64 *data)
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{
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int i;
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for (i = 0; i < 16; i++) {
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u64 tag_val, data_val;
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const char *type_str;
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tag_val = tag[i];
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if (!(tag_val & PSYCHO_IOMMU_TAG_ERR))
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continue;
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data_val = data[i];
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switch((tag_val & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
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case 0:
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type_str = "Protection Error";
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break;
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case 1:
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type_str = "Invalid Error";
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break;
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case 2:
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type_str = "TimeOut Error";
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break;
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case 3:
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default:
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type_str = "ECC Error";
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break;
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}
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printk(KERN_ERR "%s: IOMMU TAG(%d)[error(%s) wr(%d) "
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"str(%d) sz(%dK) vpg(%08llx)]\n",
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pbm->name, i, type_str,
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((tag_val & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
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((tag_val & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
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((tag_val & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
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(tag_val & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
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printk(KERN_ERR "%s: IOMMU DATA(%d)[valid(%d) cache(%d) "
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"ppg(%016llx)]\n",
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pbm->name, i,
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((data_val & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
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((data_val & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
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(data_val & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
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}
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}
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#define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL
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#define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL
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void psycho_check_iommu_error(struct pci_pbm_info *pbm,
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unsigned long afsr,
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unsigned long afar,
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enum psycho_error_type type)
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{
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u64 control, iommu_tag[16], iommu_data[16];
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struct iommu *iommu = pbm->iommu;
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unsigned long flags;
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spin_lock_irqsave(&iommu->lock, flags);
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control = upa_readq(iommu->iommu_control);
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if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
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const char *type_str;
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control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
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upa_writeq(control, iommu->iommu_control);
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switch ((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
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case 0:
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type_str = "Protection Error";
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break;
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case 1:
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type_str = "Invalid Error";
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break;
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case 2:
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type_str = "TimeOut Error";
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break;
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case 3:
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default:
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type_str = "ECC Error";
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break;
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}
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printk(KERN_ERR "%s: IOMMU Error, type[%s]\n",
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pbm->name, type_str);
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/* It is very possible for another DVMA to occur while
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* we do this probe, and corrupt the system further.
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* But we are so screwed at this point that we are
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* likely to crash hard anyways, so get as much
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* diagnostic information to the console as we can.
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*/
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psycho_record_iommu_tags_and_data(pbm, iommu_tag, iommu_data);
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psycho_dump_iommu_tags_and_data(pbm, iommu_tag, iommu_data);
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}
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psycho_check_stc_error(pbm);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL
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#define PSYCHO_PCICTRL_SERR 0x0000000400000000UL
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static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm)
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{
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irqreturn_t ret = IRQ_NONE;
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u64 csr, csr_error_bits;
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u16 stat, *addr;
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csr = upa_readq(pbm->pci_csr);
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csr_error_bits = csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
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if (csr_error_bits) {
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/* Clear the errors. */
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upa_writeq(csr, pbm->pci_csr);
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/* Log 'em. */
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if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
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printk(KERN_ERR "%s: PCI streaming byte hole "
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"error asserted.\n", pbm->name);
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if (csr_error_bits & PSYCHO_PCICTRL_SERR)
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printk(KERN_ERR "%s: PCI SERR signal asserted.\n",
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pbm->name);
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ret = IRQ_HANDLED;
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}
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addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
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0, PCI_STATUS);
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pci_config_read16(addr, &stat);
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if (stat & (PCI_STATUS_PARITY |
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PCI_STATUS_SIG_TARGET_ABORT |
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PCI_STATUS_REC_TARGET_ABORT |
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PCI_STATUS_REC_MASTER_ABORT |
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PCI_STATUS_SIG_SYSTEM_ERROR)) {
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printk(KERN_ERR "%s: PCI bus error, PCI_STATUS[%04x]\n",
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pbm->name, stat);
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pci_config_write16(addr, 0xffff);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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#define PSYCHO_PCIAFSR_PMA 0x8000000000000000ULL
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#define PSYCHO_PCIAFSR_PTA 0x4000000000000000ULL
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#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000ULL
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#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000ULL
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#define PSYCHO_PCIAFSR_SMA 0x0800000000000000ULL
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#define PSYCHO_PCIAFSR_STA 0x0400000000000000ULL
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#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000ULL
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#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000ULL
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#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000ULL
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#define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000ULL
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#define PSYCHO_PCIAFSR_BLK 0x0000000080000000ULL
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#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000ULL
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#define PSYCHO_PCIAFSR_MID 0x000000003e000000ULL
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#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffULL
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irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
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{
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struct pci_pbm_info *pbm = dev_id;
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u64 afsr, afar, error_bits;
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int reported;
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afsr = upa_readq(pbm->pci_afsr);
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afar = upa_readq(pbm->pci_afar);
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error_bits = afsr &
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(PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
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PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
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PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
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PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
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if (!error_bits)
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return psycho_pcierr_intr_other(pbm);
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upa_writeq(error_bits, pbm->pci_afsr);
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printk(KERN_ERR "%s: PCI Error, primary error type[%s]\n",
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pbm->name,
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(((error_bits & PSYCHO_PCIAFSR_PMA) ?
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"Master Abort" :
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((error_bits & PSYCHO_PCIAFSR_PTA) ?
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"Target Abort" :
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((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
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"Excessive Retries" :
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((error_bits & PSYCHO_PCIAFSR_PPERR) ?
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"Parity Error" : "???"))))));
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printk(KERN_ERR "%s: bytemask[%04llx] UPA_MID[%02llx] was_block(%d)\n",
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pbm->name,
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(afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
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(afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
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(afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
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printk(KERN_ERR "%s: PCI AFAR [%016llx]\n", pbm->name, afar);
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printk(KERN_ERR "%s: PCI Secondary errors [", pbm->name);
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reported = 0;
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if (afsr & PSYCHO_PCIAFSR_SMA) {
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reported++;
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printk("(Master Abort)");
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}
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if (afsr & PSYCHO_PCIAFSR_STA) {
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reported++;
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printk("(Target Abort)");
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}
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if (afsr & PSYCHO_PCIAFSR_SRTRY) {
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reported++;
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printk("(Excessive Retries)");
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}
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if (afsr & PSYCHO_PCIAFSR_SPERR) {
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reported++;
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printk("(Parity Error)");
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}
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if (!reported)
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printk("(none)");
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printk("]\n");
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if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
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psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
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pci_scan_for_target_abort(pbm, pbm->pci_bus);
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}
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if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
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pci_scan_for_master_abort(pbm, pbm->pci_bus);
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if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
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pci_scan_for_parity_error(pbm, pbm->pci_bus);
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return IRQ_HANDLED;
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}
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static void psycho_iommu_flush(struct pci_pbm_info *pbm)
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{
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int i;
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for (i = 0; i < 16; i++) {
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unsigned long off = i * 8;
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upa_writeq(0, pbm->controller_regs + PSYCHO_IOMMU_TAG + off);
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upa_writeq(0, pbm->controller_regs + PSYCHO_IOMMU_DATA + off);
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}
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}
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#define PSYCHO_IOMMU_CONTROL 0x0200UL
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#define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL
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#define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL
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#define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL
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#define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL
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#define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL
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#define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL
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#define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL
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#define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL
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#define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL
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#define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL
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#define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL
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#define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL
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#define PSYCHO_IOMMU_FLUSH 0x0210UL
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#define PSYCHO_IOMMU_TSBBASE 0x0208UL
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int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize,
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u32 dvma_offset, u32 dma_mask,
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unsigned long write_complete_offset)
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{
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struct iommu *iommu = pbm->iommu;
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u64 control;
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int err;
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iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL;
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iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE;
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iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH;
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iommu->iommu_tags = pbm->controller_regs + PSYCHO_IOMMU_TAG;
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iommu->write_complete_reg = (pbm->controller_regs +
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write_complete_offset);
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iommu->iommu_ctxflush = 0;
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control = upa_readq(iommu->iommu_control);
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control |= PSYCHO_IOMMU_CTRL_DENAB;
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upa_writeq(control, iommu->iommu_control);
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psycho_iommu_flush(pbm);
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/* Leave diag mode enabled for full-flushing done in pci_iommu.c */
|
|
err = iommu_table_init(iommu, tsbsize * 1024 * 8,
|
|
dvma_offset, dma_mask, pbm->numa_node);
|
|
if (err)
|
|
return err;
|
|
|
|
upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
|
|
|
|
control = upa_readq(iommu->iommu_control);
|
|
control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
|
|
control |= PSYCHO_IOMMU_CTRL_ENAB;
|
|
|
|
switch (tsbsize) {
|
|
case 64:
|
|
control |= PSYCHO_IOMMU_TSBSZ_64K;
|
|
break;
|
|
case 128:
|
|
control |= PSYCHO_IOMMU_TSBSZ_128K;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
upa_writeq(control, iommu->iommu_control);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
void psycho_pbm_init_common(struct pci_pbm_info *pbm, struct platform_device *op,
|
|
const char *chip_name, int chip_type)
|
|
{
|
|
struct device_node *dp = op->dev.of_node;
|
|
|
|
pbm->name = dp->full_name;
|
|
pbm->numa_node = NUMA_NO_NODE;
|
|
pbm->chip_type = chip_type;
|
|
pbm->chip_version = of_getintprop_default(dp, "version#", 0);
|
|
pbm->chip_revision = of_getintprop_default(dp, "module-revision#", 0);
|
|
pbm->op = op;
|
|
pbm->pci_ops = &sun4u_pci_ops;
|
|
pbm->config_space_reg_bits = 8;
|
|
pbm->index = pci_num_pbms++;
|
|
pci_get_pbm_props(pbm);
|
|
pci_determine_mem_io_space(pbm);
|
|
|
|
printk(KERN_INFO "%s: %s PCI Bus Module ver[%x:%x]\n",
|
|
pbm->name, chip_name,
|
|
pbm->chip_version, pbm->chip_revision);
|
|
}
|