676 lines
18 KiB
ArmAsm
676 lines
18 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
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*
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* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
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* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
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* Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
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* Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
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* Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
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*/
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#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <linux/init.h>
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#include <linux/pgtable.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/msr.h>
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#include <asm/cache.h>
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#include <asm/processor-flags.h>
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#include <asm/percpu.h>
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#include <asm/nops.h>
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#include "../entry/calling.h"
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#include <asm/export.h>
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#include <asm/nospec-branch.h>
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#include <asm/fixmap.h>
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/*
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* We are not able to switch in one step to the final KERNEL ADDRESS SPACE
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* because we need identity-mapped pages.
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*/
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#define l4_index(x) (((x) >> 39) & 511)
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#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
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L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
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L4_START_KERNEL = l4_index(__START_KERNEL_map)
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L3_START_KERNEL = pud_index(__START_KERNEL_map)
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.text
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__HEAD
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.code64
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SYM_CODE_START_NOALIGN(startup_64)
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UNWIND_HINT_EMPTY
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/*
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* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
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* and someone has loaded an identity mapped page table
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* for us. These identity mapped page tables map all of the
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* kernel pages and possibly all of memory.
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*
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* %rsi holds a physical pointer to real_mode_data.
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*
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* We come here either directly from a 64bit bootloader, or from
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* arch/x86/boot/compressed/head_64.S.
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*
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* We only come here initially at boot nothing else comes here.
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*
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* Since we may be loaded at an address different from what we were
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* compiled to run at we first fixup the physical addresses in our page
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* tables and then reload them.
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*/
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/* Set up the stack for verify_cpu(), similar to initial_stack below */
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leaq (__end_init_task - FRAME_SIZE)(%rip), %rsp
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leaq _text(%rip), %rdi
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/*
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* initial_gs points to initial fixed_percpu_data struct with storage for
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* the stack protector canary. Global pointer fixups are needed at this
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* stage, so apply them as is done in fixup_pointer(), and initialize %gs
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* such that the canary can be accessed at %gs:40 for subsequent C calls.
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*/
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movl $MSR_GS_BASE, %ecx
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movq initial_gs(%rip), %rax
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movq $_text, %rdx
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subq %rdx, %rax
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addq %rdi, %rax
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movq %rax, %rdx
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shrq $32, %rdx
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wrmsr
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pushq %rsi
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call startup_64_setup_env
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popq %rsi
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/* Now switch to __KERNEL_CS so IRET works reliably */
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pushq $__KERNEL_CS
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leaq .Lon_kernel_cs(%rip), %rax
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pushq %rax
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lretq
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.Lon_kernel_cs:
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UNWIND_HINT_EMPTY
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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/*
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* Activate SEV/SME memory encryption if supported/enabled. This needs to
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* be done now, since this also includes setup of the SEV-SNP CPUID table,
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* which needs to be done before any CPUID instructions are executed in
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* subsequent code.
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*/
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movq %rsi, %rdi
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pushq %rsi
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call sme_enable
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popq %rsi
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#endif
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/* Sanitize CPU configuration */
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call verify_cpu
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/*
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* Perform pagetable fixups. Additionally, if SME is active, encrypt
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* the kernel and retrieve the modifier (SME encryption mask if SME
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* is active) to be added to the initial pgdir entry that will be
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* programmed into CR3.
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*/
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leaq _text(%rip), %rdi
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pushq %rsi
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call __startup_64
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popq %rsi
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/* Form the CR3 value being sure to include the CR3 modifier */
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addq $(early_top_pgt - __START_KERNEL_map), %rax
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jmp 1f
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SYM_CODE_END(startup_64)
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SYM_CODE_START(secondary_startup_64)
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UNWIND_HINT_EMPTY
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ANNOTATE_NOENDBR
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/*
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* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
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* and someone has loaded a mapped page table.
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*
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* %rsi holds a physical pointer to real_mode_data.
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*
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* We come here either from startup_64 (using physical addresses)
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* or from trampoline.S (using virtual addresses).
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*
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* Using virtual addresses from trampoline.S removes the need
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* to have any identity mapped pages in the kernel page table
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* after the boot processor executes this code.
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*/
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/* Sanitize CPU configuration */
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call verify_cpu
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/*
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* The secondary_startup_64_no_verify entry point is only used by
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* SEV-ES guests. In those guests the call to verify_cpu() would cause
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* #VC exceptions which can not be handled at this stage of secondary
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* CPU bringup.
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*
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* All non SEV-ES systems, especially Intel systems, need to execute
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* verify_cpu() above to make sure NX is enabled.
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*/
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SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
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UNWIND_HINT_EMPTY
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ANNOTATE_NOENDBR
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/*
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* Retrieve the modifier (SME encryption mask if SME is active) to be
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* added to the initial pgdir entry that will be programmed into CR3.
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*/
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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movq sme_me_mask, %rax
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#else
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xorq %rax, %rax
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#endif
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/* Form the CR3 value being sure to include the CR3 modifier */
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addq $(init_top_pgt - __START_KERNEL_map), %rax
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1:
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#ifdef CONFIG_X86_MCE
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/*
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* Preserve CR4.MCE if the kernel will enable #MC support.
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* Clearing MCE may fault in some environments (that also force #MC
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* support). Any machine check that occurs before #MC support is fully
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* configured will crash the system regardless of the CR4.MCE value set
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* here.
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*/
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movq %cr4, %rcx
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andl $X86_CR4_MCE, %ecx
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#else
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movl $0, %ecx
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#endif
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/* Enable PAE mode, PGE and LA57 */
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orl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
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#ifdef CONFIG_X86_5LEVEL
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testl $1, __pgtable_l5_enabled(%rip)
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jz 1f
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orl $X86_CR4_LA57, %ecx
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1:
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#endif
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movq %rcx, %cr4
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/* Setup early boot stage 4-/5-level pagetables. */
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addq phys_base(%rip), %rax
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/*
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* For SEV guests: Verify that the C-bit is correct. A malicious
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* hypervisor could lie about the C-bit position to perform a ROP
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* attack on the guest by writing to the unencrypted stack and wait for
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* the next RET instruction.
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* %rsi carries pointer to realmode data and is callee-clobbered. Save
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* and restore it.
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*/
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pushq %rsi
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movq %rax, %rdi
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call sev_verify_cbit
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popq %rsi
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/*
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* Switch to new page-table
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*
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* For the boot CPU this switches to early_top_pgt which still has the
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* indentity mappings present. The secondary CPUs will switch to the
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* init_top_pgt here, away from the trampoline_pgd and unmap the
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* indentity mapped ranges.
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*/
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movq %rax, %cr3
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/*
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* Do a global TLB flush after the CR3 switch to make sure the TLB
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* entries from the identity mapping are flushed.
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*/
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movq %cr4, %rcx
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movq %rcx, %rax
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xorq $X86_CR4_PGE, %rcx
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movq %rcx, %cr4
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movq %rax, %cr4
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/* Ensure I am executing from virtual addresses */
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movq $1f, %rax
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ANNOTATE_RETPOLINE_SAFE
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jmp *%rax
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1:
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UNWIND_HINT_EMPTY
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ANNOTATE_NOENDBR // above
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/*
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* We must switch to a new descriptor in kernel space for the GDT
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* because soon the kernel won't have access anymore to the userspace
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* addresses where we're currently running on. We have to do that here
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* because in 32bit we couldn't load a 64bit linear address.
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*/
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lgdt early_gdt_descr(%rip)
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/* set up data segments */
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xorl %eax,%eax
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movl %eax,%ds
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movl %eax,%ss
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movl %eax,%es
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/*
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* We don't really need to load %fs or %gs, but load them anyway
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* to kill any stale realmode selectors. This allows execution
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* under VT hardware.
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*/
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movl %eax,%fs
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movl %eax,%gs
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/* Set up %gs.
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*
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* The base of %gs always points to fixed_percpu_data. If the
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* stack protector canary is enabled, it is located at %gs:40.
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* Note that, on SMP, the boot cpu uses init data section until
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* the per cpu areas are set up.
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*/
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movl $MSR_GS_BASE,%ecx
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movl initial_gs(%rip),%eax
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movl initial_gs+4(%rip),%edx
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wrmsr
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/*
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* Setup a boot time stack - Any secondary CPU will have lost its stack
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* by now because the cr3-switch above unmaps the real-mode stack
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*/
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movq initial_stack(%rip), %rsp
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/* Setup and Load IDT */
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pushq %rsi
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call early_setup_idt
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popq %rsi
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/* Check if nx is implemented */
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movl $0x80000001, %eax
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cpuid
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movl %edx,%edi
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/* Setup EFER (Extended Feature Enable Register) */
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movl $MSR_EFER, %ecx
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rdmsr
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/*
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* Preserve current value of EFER for comparison and to skip
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* EFER writes if no change was made (for TDX guest)
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*/
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movl %eax, %edx
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btsl $_EFER_SCE, %eax /* Enable System Call */
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btl $20,%edi /* No Execute supported? */
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jnc 1f
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btsl $_EFER_NX, %eax
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btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
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/* Avoid writing EFER if no change was made (for TDX guest) */
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1: cmpl %edx, %eax
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je 1f
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xor %edx, %edx
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wrmsr /* Make changes effective */
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1:
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/* Setup cr0 */
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movl $CR0_STATE, %eax
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/* Make changes effective */
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movq %rax, %cr0
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/* zero EFLAGS after setting rsp */
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pushq $0
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popfq
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/* rsi is pointer to real mode structure with interesting info.
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pass it to C */
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movq %rsi, %rdi
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.Ljump_to_C_code:
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/*
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* Jump to run C code and to be on a real kernel address.
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* Since we are running on identity-mapped space we have to jump
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* to the full 64bit address, this is only possible as indirect
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* jump. In addition we need to ensure %cs is set so we make this
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* a far return.
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*
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* Note: do not change to far jump indirect with 64bit offset.
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*
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* AMD does not support far jump indirect with 64bit offset.
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* AMD64 Architecture Programmer's Manual, Volume 3: states only
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* JMP FAR mem16:16 FF /5 Far jump indirect,
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* with the target specified by a far pointer in memory.
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* JMP FAR mem16:32 FF /5 Far jump indirect,
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* with the target specified by a far pointer in memory.
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*
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* Intel64 does support 64bit offset.
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* Software Developer Manual Vol 2: states:
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* FF /5 JMP m16:16 Jump far, absolute indirect,
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* address given in m16:16
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* FF /5 JMP m16:32 Jump far, absolute indirect,
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* address given in m16:32.
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* REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
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* address given in m16:64.
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*/
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pushq $.Lafter_lret # put return address on stack for unwinder
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xorl %ebp, %ebp # clear frame pointer
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movq initial_code(%rip), %rax
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pushq $__KERNEL_CS # set correct cs
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pushq %rax # target address in negative space
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lretq
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.Lafter_lret:
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ANNOTATE_NOENDBR
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SYM_CODE_END(secondary_startup_64)
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#include "verify_cpu.S"
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#include "sev_verify_cbit.S"
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#ifdef CONFIG_HOTPLUG_CPU
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/*
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* Boot CPU0 entry point. It's called from play_dead(). Everything has been set
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* up already except stack. We just set up stack here. Then call
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* start_secondary() via .Ljump_to_C_code.
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*/
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SYM_CODE_START(start_cpu0)
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ANNOTATE_NOENDBR
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UNWIND_HINT_EMPTY
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movq initial_stack(%rip), %rsp
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jmp .Ljump_to_C_code
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SYM_CODE_END(start_cpu0)
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#endif
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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/*
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* VC Exception handler used during early boot when running on kernel
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* addresses, but before the switch to the idt_table can be made.
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* The early_idt_handler_array can't be used here because it calls into a lot
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* of __init code and this handler is also used during CPU offlining/onlining.
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* Therefore this handler ends up in the .text section so that it stays around
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* when .init.text is freed.
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*/
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SYM_CODE_START_NOALIGN(vc_boot_ghcb)
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UNWIND_HINT_IRET_REGS offset=8
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ENDBR
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ANNOTATE_UNRET_END
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/* Build pt_regs */
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PUSH_AND_CLEAR_REGS
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/* Call C handler */
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movq %rsp, %rdi
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movq ORIG_RAX(%rsp), %rsi
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movq initial_vc_handler(%rip), %rax
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ANNOTATE_RETPOLINE_SAFE
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call *%rax
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/* Unwind pt_regs */
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POP_REGS
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/* Remove Error Code */
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addq $8, %rsp
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iretq
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SYM_CODE_END(vc_boot_ghcb)
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#endif
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/* Both SMP bootup and ACPI suspend change these variables */
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__REFDATA
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.balign 8
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SYM_DATA(initial_code, .quad x86_64_start_kernel)
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SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data))
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb)
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#endif
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/*
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* The FRAME_SIZE gap is a convention which helps the in-kernel unwinder
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* reliably detect the end of the stack.
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*/
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SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - FRAME_SIZE)
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__FINITDATA
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__INIT
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SYM_CODE_START(early_idt_handler_array)
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i = 0
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.rept NUM_EXCEPTION_VECTORS
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.if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
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UNWIND_HINT_IRET_REGS
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ENDBR
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pushq $0 # Dummy error code, to make stack frame uniform
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.else
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UNWIND_HINT_IRET_REGS offset=8
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ENDBR
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.endif
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pushq $i # 72(%rsp) Vector number
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jmp early_idt_handler_common
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UNWIND_HINT_IRET_REGS
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i = i + 1
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.fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
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.endr
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SYM_CODE_END(early_idt_handler_array)
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ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS]
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SYM_CODE_START_LOCAL(early_idt_handler_common)
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UNWIND_HINT_IRET_REGS offset=16
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ANNOTATE_UNRET_END
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/*
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* The stack is the hardware frame, an error code or zero, and the
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* vector number.
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*/
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cld
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incl early_recursion_flag(%rip)
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/* The vector number is currently in the pt_regs->di slot. */
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pushq %rsi /* pt_regs->si */
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movq 8(%rsp), %rsi /* RSI = vector number */
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movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
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pushq %rdx /* pt_regs->dx */
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pushq %rcx /* pt_regs->cx */
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pushq %rax /* pt_regs->ax */
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pushq %r8 /* pt_regs->r8 */
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pushq %r9 /* pt_regs->r9 */
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pushq %r10 /* pt_regs->r10 */
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pushq %r11 /* pt_regs->r11 */
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pushq %rbx /* pt_regs->bx */
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pushq %rbp /* pt_regs->bp */
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pushq %r12 /* pt_regs->r12 */
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pushq %r13 /* pt_regs->r13 */
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pushq %r14 /* pt_regs->r14 */
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pushq %r15 /* pt_regs->r15 */
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UNWIND_HINT_REGS
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movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
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call do_early_exception
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decl early_recursion_flag(%rip)
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jmp restore_regs_and_return_to_kernel
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SYM_CODE_END(early_idt_handler_common)
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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/*
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* VC Exception handler used during very early boot. The
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* early_idt_handler_array can't be used because it returns via the
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* paravirtualized INTERRUPT_RETURN and pv-ops don't work that early.
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*
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* XXX it does, fix this.
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*
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* This handler will end up in the .init.text section and not be
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* available to boot secondary CPUs.
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*/
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SYM_CODE_START_NOALIGN(vc_no_ghcb)
|
|
UNWIND_HINT_IRET_REGS offset=8
|
|
ENDBR
|
|
|
|
ANNOTATE_UNRET_END
|
|
|
|
/* Build pt_regs */
|
|
PUSH_AND_CLEAR_REGS
|
|
|
|
/* Call C handler */
|
|
movq %rsp, %rdi
|
|
movq ORIG_RAX(%rsp), %rsi
|
|
call do_vc_no_ghcb
|
|
|
|
/* Unwind pt_regs */
|
|
POP_REGS
|
|
|
|
/* Remove Error Code */
|
|
addq $8, %rsp
|
|
|
|
/* Pure iret required here - don't use INTERRUPT_RETURN */
|
|
iretq
|
|
SYM_CODE_END(vc_no_ghcb)
|
|
#endif
|
|
|
|
#define SYM_DATA_START_PAGE_ALIGNED(name) \
|
|
SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE)
|
|
|
|
#ifdef CONFIG_PAGE_TABLE_ISOLATION
|
|
/*
|
|
* Each PGD needs to be 8k long and 8k aligned. We do not
|
|
* ever go out to userspace with these, so we do not
|
|
* strictly *need* the second page, but this allows us to
|
|
* have a single set_pgd() implementation that does not
|
|
* need to worry about whether it has 4k or 8k to work
|
|
* with.
|
|
*
|
|
* This ensures PGDs are 8k long:
|
|
*/
|
|
#define PTI_USER_PGD_FILL 512
|
|
/* This ensures they are 8k-aligned: */
|
|
#define SYM_DATA_START_PTI_ALIGNED(name) \
|
|
SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE)
|
|
#else
|
|
#define SYM_DATA_START_PTI_ALIGNED(name) \
|
|
SYM_DATA_START_PAGE_ALIGNED(name)
|
|
#define PTI_USER_PGD_FILL 0
|
|
#endif
|
|
|
|
/* Automate the creation of 1 to 1 mapping pmd entries */
|
|
#define PMDS(START, PERM, COUNT) \
|
|
i = 0 ; \
|
|
.rept (COUNT) ; \
|
|
.quad (START) + (i << PMD_SHIFT) + (PERM) ; \
|
|
i = i + 1 ; \
|
|
.endr
|
|
|
|
__INITDATA
|
|
.balign 4
|
|
|
|
SYM_DATA_START_PTI_ALIGNED(early_top_pgt)
|
|
.fill 512,8,0
|
|
.fill PTI_USER_PGD_FILL,8,0
|
|
SYM_DATA_END(early_top_pgt)
|
|
|
|
SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts)
|
|
.fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
|
|
SYM_DATA_END(early_dynamic_pgts)
|
|
|
|
SYM_DATA(early_recursion_flag, .long 0)
|
|
|
|
.data
|
|
|
|
#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH)
|
|
SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
|
|
.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
|
|
.org init_top_pgt + L4_PAGE_OFFSET*8, 0
|
|
.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
|
|
.org init_top_pgt + L4_START_KERNEL*8, 0
|
|
/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
|
|
.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
|
|
.fill PTI_USER_PGD_FILL,8,0
|
|
SYM_DATA_END(init_top_pgt)
|
|
|
|
SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt)
|
|
.quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
|
|
.fill 511, 8, 0
|
|
SYM_DATA_END(level3_ident_pgt)
|
|
SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt)
|
|
/*
|
|
* Since I easily can, map the first 1G.
|
|
* Don't set NX because code runs from these pages.
|
|
*
|
|
* Note: This sets _PAGE_GLOBAL despite whether
|
|
* the CPU supports it or it is enabled. But,
|
|
* the CPU should ignore the bit.
|
|
*/
|
|
PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
|
|
SYM_DATA_END(level2_ident_pgt)
|
|
#else
|
|
SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
|
|
.fill 512,8,0
|
|
.fill PTI_USER_PGD_FILL,8,0
|
|
SYM_DATA_END(init_top_pgt)
|
|
#endif
|
|
|
|
#ifdef CONFIG_X86_5LEVEL
|
|
SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt)
|
|
.fill 511,8,0
|
|
.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
|
|
SYM_DATA_END(level4_kernel_pgt)
|
|
#endif
|
|
|
|
SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt)
|
|
.fill L3_START_KERNEL,8,0
|
|
/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
|
|
.quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
|
|
.quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
|
|
SYM_DATA_END(level3_kernel_pgt)
|
|
|
|
SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt)
|
|
/*
|
|
* Kernel high mapping.
|
|
*
|
|
* The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in
|
|
* virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled,
|
|
* 512 MiB otherwise.
|
|
*
|
|
* (NOTE: after that starts the module area, see MODULES_VADDR.)
|
|
*
|
|
* This table is eventually used by the kernel during normal runtime.
|
|
* Care must be taken to clear out undesired bits later, like _PAGE_RW
|
|
* or _PAGE_GLOBAL in some cases.
|
|
*/
|
|
PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE)
|
|
SYM_DATA_END(level2_kernel_pgt)
|
|
|
|
SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt)
|
|
.fill (512 - 4 - FIXMAP_PMD_NUM),8,0
|
|
pgtno = 0
|
|
.rept (FIXMAP_PMD_NUM)
|
|
.quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \
|
|
+ _PAGE_TABLE_NOENC;
|
|
pgtno = pgtno + 1
|
|
.endr
|
|
/* 6 MB reserved space + a 2MB hole */
|
|
.fill 4,8,0
|
|
SYM_DATA_END(level2_fixmap_pgt)
|
|
|
|
SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt)
|
|
.rept (FIXMAP_PMD_NUM)
|
|
.fill 512,8,0
|
|
.endr
|
|
SYM_DATA_END(level1_fixmap_pgt)
|
|
|
|
#undef PMDS
|
|
|
|
.data
|
|
.align 16
|
|
|
|
SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1)
|
|
SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page))
|
|
|
|
.align 16
|
|
/* This must match the first entry in level2_kernel_pgt */
|
|
SYM_DATA(phys_base, .quad 0x0)
|
|
EXPORT_SYMBOL(phys_base)
|
|
|
|
#include "../../x86/xen/xen-head.S"
|
|
|
|
__PAGE_ALIGNED_BSS
|
|
SYM_DATA_START_PAGE_ALIGNED(empty_zero_page)
|
|
.skip PAGE_SIZE
|
|
SYM_DATA_END(empty_zero_page)
|
|
EXPORT_SYMBOL(empty_zero_page)
|
|
|