196 lines
4.9 KiB
C
196 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020-2023 Intel Corporation
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*/
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#ifndef __IVPU_DRV_H__
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#define __IVPU_DRV_H__
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#include <drm/drm_device.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_managed.h>
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#include <drm/drm_mm.h>
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#include <drm/drm_print.h>
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#include <linux/pci.h>
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#include <linux/xarray.h>
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#include <uapi/drm/ivpu_accel.h>
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#include "ivpu_mmu_context.h"
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#define DRIVER_NAME "intel_vpu"
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#define DRIVER_DESC "Driver for Intel Versatile Processing Unit (VPU)"
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#define DRIVER_DATE "20230117"
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#define PCI_DEVICE_ID_MTL 0x7d1d
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#define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
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/* SSID 1 is used by the VPU to represent invalid context */
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#define IVPU_USER_CONTEXT_MIN_SSID 2
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#define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63)
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#define IVPU_NUM_ENGINES 2
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#define IVPU_PLATFORM_SILICON 0
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#define IVPU_PLATFORM_SIMICS 2
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#define IVPU_PLATFORM_FPGA 3
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#define IVPU_PLATFORM_INVALID 8
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#define IVPU_DBG_REG BIT(0)
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#define IVPU_DBG_IRQ BIT(1)
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#define IVPU_DBG_MMU BIT(2)
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#define IVPU_DBG_FILE BIT(3)
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#define IVPU_DBG_MISC BIT(4)
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#define IVPU_DBG_FW_BOOT BIT(5)
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#define IVPU_DBG_PM BIT(6)
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#define IVPU_DBG_IPC BIT(7)
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#define IVPU_DBG_BO BIT(8)
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#define IVPU_DBG_JOB BIT(9)
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#define IVPU_DBG_JSM BIT(10)
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#define IVPU_DBG_KREF BIT(11)
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#define IVPU_DBG_RPM BIT(12)
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#define ivpu_err(vdev, fmt, ...) \
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drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
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#define ivpu_err_ratelimited(vdev, fmt, ...) \
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drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
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#define ivpu_warn(vdev, fmt, ...) \
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drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
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#define ivpu_warn_ratelimited(vdev, fmt, ...) \
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drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
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#define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
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#define ivpu_dbg(vdev, type, fmt, args...) do { \
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if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
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dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
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} while (0)
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#define IVPU_WA(wa_name) (vdev->wa.wa_name)
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struct ivpu_wa_table {
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bool punit_disabled;
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bool clear_runtime_mem;
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bool d3hot_after_power_off;
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};
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struct ivpu_hw_info;
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struct ivpu_mmu_info;
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struct ivpu_fw_info;
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struct ivpu_ipc_info;
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struct ivpu_pm_info;
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struct ivpu_device {
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struct drm_device drm;
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void __iomem *regb;
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void __iomem *regv;
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u32 platform;
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u32 irq;
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struct ivpu_wa_table wa;
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struct ivpu_hw_info *hw;
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struct ivpu_mmu_info *mmu;
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struct ivpu_fw_info *fw;
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struct ivpu_ipc_info *ipc;
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struct ivpu_pm_info *pm;
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struct ivpu_mmu_context gctx;
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struct xarray context_xa;
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struct xa_limit context_xa_limit;
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struct xarray submitted_jobs_xa;
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struct task_struct *job_done_thread;
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atomic64_t unique_id_counter;
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struct {
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int boot;
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int jsm;
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int tdr;
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int reschedule_suspend;
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} timeout;
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};
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/*
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* file_priv has its own refcount (ref) that allows user space to close the fd
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* without blocking even if VPU is still processing some jobs.
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*/
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struct ivpu_file_priv {
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struct kref ref;
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struct ivpu_device *vdev;
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struct mutex lock; /* Protects cmdq */
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struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES];
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struct ivpu_mmu_context ctx;
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u32 priority;
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bool has_mmu_faults;
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};
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extern int ivpu_dbg_mask;
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extern u8 ivpu_pll_min_ratio;
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extern u8 ivpu_pll_max_ratio;
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#define IVPU_TEST_MODE_DISABLED 0
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#define IVPU_TEST_MODE_FW_TEST 1
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#define IVPU_TEST_MODE_NULL_HW 2
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extern int ivpu_test_mode;
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struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
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struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id);
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void ivpu_file_priv_put(struct ivpu_file_priv **link);
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int ivpu_boot(struct ivpu_device *vdev);
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int ivpu_shutdown(struct ivpu_device *vdev);
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static inline bool ivpu_is_mtl(struct ivpu_device *vdev)
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{
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return to_pci_dev(vdev->drm.dev)->device == PCI_DEVICE_ID_MTL;
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}
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static inline u8 ivpu_revision(struct ivpu_device *vdev)
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{
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return to_pci_dev(vdev->drm.dev)->revision;
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}
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static inline u16 ivpu_device_id(struct ivpu_device *vdev)
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{
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return to_pci_dev(vdev->drm.dev)->device;
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}
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static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
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{
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return container_of(dev, struct ivpu_device, drm);
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}
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static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
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{
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struct xa_limit ctx_limit = vdev->context_xa_limit;
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return (ctx_limit.max - ctx_limit.min + 1);
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}
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static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
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{
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WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
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return vdev->platform;
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}
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static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
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{
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return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
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}
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static inline bool ivpu_is_simics(struct ivpu_device *vdev)
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{
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return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
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}
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static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
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{
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return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
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}
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#endif /* __IVPU_DRV_H__ */
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