516 lines
14 KiB
C
516 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/at91.h>
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#include "pmc.h"
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struct sck {
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char *n;
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char *p;
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u8 id;
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};
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struct pck {
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char *n;
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u8 id;
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};
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struct at91sam926x_data {
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const struct clk_pll_layout *plla_layout;
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const struct clk_pll_characteristics *plla_characteristics;
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const struct clk_pll_layout *pllb_layout;
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const struct clk_pll_characteristics *pllb_characteristics;
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const struct clk_master_characteristics *mck_characteristics;
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const struct sck *sck;
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const struct pck *pck;
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u8 num_sck;
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u8 num_pck;
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u8 num_progck;
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bool has_slck;
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};
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static DEFINE_SPINLOCK(at91sam9260_mck_lock);
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static const struct clk_master_characteristics sam9260_mck_characteristics = {
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.output = { .min = 0, .max = 105000000 },
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.divisors = { 1, 2, 4, 0 },
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};
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static u8 sam9260_plla_out[] = { 0, 2 };
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static u16 sam9260_plla_icpll[] = { 1, 1 };
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static const struct clk_range sam9260_plla_outputs[] = {
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{ .min = 80000000, .max = 160000000 },
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{ .min = 150000000, .max = 240000000 },
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};
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static const struct clk_pll_characteristics sam9260_plla_characteristics = {
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.input = { .min = 1000000, .max = 32000000 },
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.num_output = ARRAY_SIZE(sam9260_plla_outputs),
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.output = sam9260_plla_outputs,
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.icpll = sam9260_plla_icpll,
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.out = sam9260_plla_out,
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};
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static u8 sam9260_pllb_out[] = { 1 };
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static u16 sam9260_pllb_icpll[] = { 1 };
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static const struct clk_range sam9260_pllb_outputs[] = {
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{ .min = 70000000, .max = 130000000 },
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};
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static const struct clk_pll_characteristics sam9260_pllb_characteristics = {
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.input = { .min = 1000000, .max = 5000000 },
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.num_output = ARRAY_SIZE(sam9260_pllb_outputs),
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.output = sam9260_pllb_outputs,
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.icpll = sam9260_pllb_icpll,
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.out = sam9260_pllb_out,
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};
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static const struct sck at91sam9260_systemck[] = {
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{ .n = "uhpck", .p = "usbck", .id = 6 },
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{ .n = "udpck", .p = "usbck", .id = 7 },
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{ .n = "pck0", .p = "prog0", .id = 8 },
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{ .n = "pck1", .p = "prog1", .id = 9 },
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};
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static const struct pck at91sam9260_periphck[] = {
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{ .n = "pioA_clk", .id = 2 },
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{ .n = "pioB_clk", .id = 3 },
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{ .n = "pioC_clk", .id = 4 },
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{ .n = "adc_clk", .id = 5 },
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{ .n = "usart0_clk", .id = 6 },
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{ .n = "usart1_clk", .id = 7 },
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{ .n = "usart2_clk", .id = 8 },
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{ .n = "mci0_clk", .id = 9 },
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{ .n = "udc_clk", .id = 10 },
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{ .n = "twi0_clk", .id = 11 },
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{ .n = "spi0_clk", .id = 12 },
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{ .n = "spi1_clk", .id = 13 },
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{ .n = "ssc0_clk", .id = 14 },
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{ .n = "tc0_clk", .id = 17 },
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{ .n = "tc1_clk", .id = 18 },
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{ .n = "tc2_clk", .id = 19 },
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{ .n = "ohci_clk", .id = 20 },
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{ .n = "macb0_clk", .id = 21 },
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{ .n = "isi_clk", .id = 22 },
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{ .n = "usart3_clk", .id = 23 },
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{ .n = "uart0_clk", .id = 24 },
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{ .n = "uart1_clk", .id = 25 },
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{ .n = "tc3_clk", .id = 26 },
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{ .n = "tc4_clk", .id = 27 },
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{ .n = "tc5_clk", .id = 28 },
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};
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static struct at91sam926x_data at91sam9260_data = {
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.plla_layout = &at91rm9200_pll_layout,
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.plla_characteristics = &sam9260_plla_characteristics,
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.pllb_layout = &at91rm9200_pll_layout,
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.pllb_characteristics = &sam9260_pllb_characteristics,
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.mck_characteristics = &sam9260_mck_characteristics,
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.sck = at91sam9260_systemck,
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.num_sck = ARRAY_SIZE(at91sam9260_systemck),
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.pck = at91sam9260_periphck,
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.num_pck = ARRAY_SIZE(at91sam9260_periphck),
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.num_progck = 2,
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.has_slck = true,
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};
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static const struct clk_master_characteristics sam9g20_mck_characteristics = {
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.output = { .min = 0, .max = 133000000 },
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.divisors = { 1, 2, 4, 6 },
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};
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static u8 sam9g20_plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
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static u16 sam9g20_plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
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static const struct clk_range sam9g20_plla_outputs[] = {
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{ .min = 745000000, .max = 800000000 },
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{ .min = 695000000, .max = 750000000 },
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{ .min = 645000000, .max = 700000000 },
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{ .min = 595000000, .max = 650000000 },
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{ .min = 545000000, .max = 600000000 },
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{ .min = 495000000, .max = 550000000 },
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{ .min = 445000000, .max = 500000000 },
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{ .min = 400000000, .max = 450000000 },
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};
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static const struct clk_pll_characteristics sam9g20_plla_characteristics = {
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.input = { .min = 2000000, .max = 32000000 },
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.num_output = ARRAY_SIZE(sam9g20_plla_outputs),
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.output = sam9g20_plla_outputs,
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.icpll = sam9g20_plla_icpll,
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.out = sam9g20_plla_out,
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};
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static u8 sam9g20_pllb_out[] = { 0 };
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static u16 sam9g20_pllb_icpll[] = { 0 };
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static const struct clk_range sam9g20_pllb_outputs[] = {
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{ .min = 30000000, .max = 100000000 },
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};
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static const struct clk_pll_characteristics sam9g20_pllb_characteristics = {
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.input = { .min = 2000000, .max = 32000000 },
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.num_output = ARRAY_SIZE(sam9g20_pllb_outputs),
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.output = sam9g20_pllb_outputs,
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.icpll = sam9g20_pllb_icpll,
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.out = sam9g20_pllb_out,
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};
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static struct at91sam926x_data at91sam9g20_data = {
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.plla_layout = &at91sam9g45_pll_layout,
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.plla_characteristics = &sam9g20_plla_characteristics,
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.pllb_layout = &at91sam9g20_pllb_layout,
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.pllb_characteristics = &sam9g20_pllb_characteristics,
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.mck_characteristics = &sam9g20_mck_characteristics,
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.sck = at91sam9260_systemck,
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.num_sck = ARRAY_SIZE(at91sam9260_systemck),
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.pck = at91sam9260_periphck,
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.num_pck = ARRAY_SIZE(at91sam9260_periphck),
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.num_progck = 2,
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.has_slck = true,
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};
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static const struct clk_master_characteristics sam9261_mck_characteristics = {
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.output = { .min = 0, .max = 94000000 },
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.divisors = { 1, 2, 4, 0 },
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};
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static const struct clk_range sam9261_plla_outputs[] = {
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{ .min = 80000000, .max = 200000000 },
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{ .min = 190000000, .max = 240000000 },
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};
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static const struct clk_pll_characteristics sam9261_plla_characteristics = {
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.input = { .min = 1000000, .max = 32000000 },
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.num_output = ARRAY_SIZE(sam9261_plla_outputs),
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.output = sam9261_plla_outputs,
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.icpll = sam9260_plla_icpll,
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.out = sam9260_plla_out,
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};
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static u8 sam9261_pllb_out[] = { 1 };
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static u16 sam9261_pllb_icpll[] = { 1 };
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static const struct clk_range sam9261_pllb_outputs[] = {
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{ .min = 70000000, .max = 130000000 },
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};
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static const struct clk_pll_characteristics sam9261_pllb_characteristics = {
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.input = { .min = 1000000, .max = 5000000 },
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.num_output = ARRAY_SIZE(sam9261_pllb_outputs),
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.output = sam9261_pllb_outputs,
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.icpll = sam9261_pllb_icpll,
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.out = sam9261_pllb_out,
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};
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static const struct sck at91sam9261_systemck[] = {
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{ .n = "uhpck", .p = "usbck", .id = 6 },
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{ .n = "udpck", .p = "usbck", .id = 7 },
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{ .n = "pck0", .p = "prog0", .id = 8 },
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{ .n = "pck1", .p = "prog1", .id = 9 },
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{ .n = "pck2", .p = "prog2", .id = 10 },
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{ .n = "pck3", .p = "prog3", .id = 11 },
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{ .n = "hclk0", .p = "masterck_div", .id = 16 },
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{ .n = "hclk1", .p = "masterck_div", .id = 17 },
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};
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static const struct pck at91sam9261_periphck[] = {
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{ .n = "pioA_clk", .id = 2, },
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{ .n = "pioB_clk", .id = 3, },
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{ .n = "pioC_clk", .id = 4, },
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{ .n = "usart0_clk", .id = 6, },
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{ .n = "usart1_clk", .id = 7, },
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{ .n = "usart2_clk", .id = 8, },
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{ .n = "mci0_clk", .id = 9, },
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{ .n = "udc_clk", .id = 10, },
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{ .n = "twi0_clk", .id = 11, },
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{ .n = "spi0_clk", .id = 12, },
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{ .n = "spi1_clk", .id = 13, },
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{ .n = "ssc0_clk", .id = 14, },
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{ .n = "ssc1_clk", .id = 15, },
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{ .n = "ssc2_clk", .id = 16, },
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{ .n = "tc0_clk", .id = 17, },
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{ .n = "tc1_clk", .id = 18, },
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{ .n = "tc2_clk", .id = 19, },
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{ .n = "ohci_clk", .id = 20, },
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{ .n = "lcd_clk", .id = 21, },
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};
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static struct at91sam926x_data at91sam9261_data = {
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.plla_layout = &at91rm9200_pll_layout,
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.plla_characteristics = &sam9261_plla_characteristics,
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.pllb_layout = &at91rm9200_pll_layout,
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.pllb_characteristics = &sam9261_pllb_characteristics,
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.mck_characteristics = &sam9261_mck_characteristics,
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.sck = at91sam9261_systemck,
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.num_sck = ARRAY_SIZE(at91sam9261_systemck),
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.pck = at91sam9261_periphck,
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.num_pck = ARRAY_SIZE(at91sam9261_periphck),
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.num_progck = 4,
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};
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static const struct clk_master_characteristics sam9263_mck_characteristics = {
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.output = { .min = 0, .max = 120000000 },
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.divisors = { 1, 2, 4, 0 },
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};
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static const struct clk_range sam9263_pll_outputs[] = {
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{ .min = 80000000, .max = 200000000 },
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{ .min = 190000000, .max = 240000000 },
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};
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static const struct clk_pll_characteristics sam9263_pll_characteristics = {
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.input = { .min = 1000000, .max = 32000000 },
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.num_output = ARRAY_SIZE(sam9263_pll_outputs),
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.output = sam9263_pll_outputs,
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.icpll = sam9260_plla_icpll,
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.out = sam9260_plla_out,
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};
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static const struct sck at91sam9263_systemck[] = {
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{ .n = "uhpck", .p = "usbck", .id = 6 },
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{ .n = "udpck", .p = "usbck", .id = 7 },
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{ .n = "pck0", .p = "prog0", .id = 8 },
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{ .n = "pck1", .p = "prog1", .id = 9 },
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{ .n = "pck2", .p = "prog2", .id = 10 },
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{ .n = "pck3", .p = "prog3", .id = 11 },
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};
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static const struct pck at91sam9263_periphck[] = {
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{ .n = "pioA_clk", .id = 2, },
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{ .n = "pioB_clk", .id = 3, },
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{ .n = "pioCDE_clk", .id = 4, },
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{ .n = "usart0_clk", .id = 7, },
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{ .n = "usart1_clk", .id = 8, },
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{ .n = "usart2_clk", .id = 9, },
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{ .n = "mci0_clk", .id = 10, },
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{ .n = "mci1_clk", .id = 11, },
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{ .n = "can_clk", .id = 12, },
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{ .n = "twi0_clk", .id = 13, },
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{ .n = "spi0_clk", .id = 14, },
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{ .n = "spi1_clk", .id = 15, },
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{ .n = "ssc0_clk", .id = 16, },
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{ .n = "ssc1_clk", .id = 17, },
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{ .n = "ac97_clk", .id = 18, },
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{ .n = "tcb_clk", .id = 19, },
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{ .n = "pwm_clk", .id = 20, },
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{ .n = "macb0_clk", .id = 21, },
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{ .n = "g2de_clk", .id = 23, },
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{ .n = "udc_clk", .id = 24, },
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{ .n = "isi_clk", .id = 25, },
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{ .n = "lcd_clk", .id = 26, },
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{ .n = "dma_clk", .id = 27, },
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{ .n = "ohci_clk", .id = 29, },
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};
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static struct at91sam926x_data at91sam9263_data = {
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.plla_layout = &at91rm9200_pll_layout,
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.plla_characteristics = &sam9263_pll_characteristics,
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.pllb_layout = &at91rm9200_pll_layout,
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.pllb_characteristics = &sam9263_pll_characteristics,
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.mck_characteristics = &sam9263_mck_characteristics,
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.sck = at91sam9263_systemck,
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.num_sck = ARRAY_SIZE(at91sam9263_systemck),
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.pck = at91sam9263_periphck,
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.num_pck = ARRAY_SIZE(at91sam9263_periphck),
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.num_progck = 4,
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};
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static void __init at91sam926x_pmc_setup(struct device_node *np,
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struct at91sam926x_data *data)
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{
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const char *slowxtal_name, *mainxtal_name;
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struct pmc_data *at91sam9260_pmc;
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u32 usb_div[] = { 1, 2, 4, 0 };
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const char *parent_names[6];
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const char *slck_name;
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struct regmap *regmap;
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struct clk_hw *hw;
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int i;
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bool bypass;
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i = of_property_match_string(np, "clock-names", "slow_xtal");
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if (i < 0)
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return;
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slowxtal_name = of_clk_get_parent_name(np, i);
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i = of_property_match_string(np, "clock-names", "main_xtal");
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if (i < 0)
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return;
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mainxtal_name = of_clk_get_parent_name(np, i);
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regmap = device_node_to_regmap(np);
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if (IS_ERR(regmap))
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return;
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at91sam9260_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
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ndck(data->sck, data->num_sck),
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ndck(data->pck, data->num_pck),
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0, data->num_progck);
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if (!at91sam9260_pmc)
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return;
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bypass = of_property_read_bool(np, "atmel,osc-bypass");
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hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
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bypass);
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if (IS_ERR(hw))
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goto err_free;
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hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
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if (IS_ERR(hw))
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goto err_free;
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at91sam9260_pmc->chws[PMC_MAIN] = hw;
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if (data->has_slck) {
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hw = clk_hw_register_fixed_rate_with_accuracy(NULL,
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"slow_rc_osc",
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NULL, 0, 32768,
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50000000);
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if (IS_ERR(hw))
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goto err_free;
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parent_names[0] = "slow_rc_osc";
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parent_names[1] = "slow_xtal";
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hw = at91_clk_register_sam9260_slow(regmap, "slck",
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parent_names, 2);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9260_pmc->chws[PMC_SLOW] = hw;
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slck_name = "slck";
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} else {
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slck_name = slowxtal_name;
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}
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hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
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data->plla_layout,
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data->plla_characteristics);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9260_pmc->chws[PMC_PLLACK] = hw;
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hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
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data->pllb_layout,
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data->pllb_characteristics);
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if (IS_ERR(hw))
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goto err_free;
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at91sam9260_pmc->chws[PMC_PLLBCK] = hw;
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parent_names[0] = slck_name;
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parent_names[1] = "mainck";
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parent_names[2] = "pllack";
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parent_names[3] = "pllbck";
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hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
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parent_names,
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&at91rm9200_master_layout,
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data->mck_characteristics,
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&at91sam9260_mck_lock);
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if (IS_ERR(hw))
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goto err_free;
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hw = at91_clk_register_master_div(regmap, "masterck_div",
|
|
"masterck_pres",
|
|
&at91rm9200_master_layout,
|
|
data->mck_characteristics,
|
|
&at91sam9260_mck_lock,
|
|
CLK_SET_RATE_GATE, 0);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
at91sam9260_pmc->chws[PMC_MCK] = hw;
|
|
|
|
hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
parent_names[0] = slck_name;
|
|
parent_names[1] = "mainck";
|
|
parent_names[2] = "pllack";
|
|
parent_names[3] = "pllbck";
|
|
for (i = 0; i < data->num_progck; i++) {
|
|
char name[6];
|
|
|
|
snprintf(name, sizeof(name), "prog%d", i);
|
|
|
|
hw = at91_clk_register_programmable(regmap, name,
|
|
parent_names, 4, i,
|
|
&at91rm9200_programmable_layout,
|
|
NULL);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
at91sam9260_pmc->pchws[i] = hw;
|
|
}
|
|
|
|
for (i = 0; i < data->num_sck; i++) {
|
|
hw = at91_clk_register_system(regmap, data->sck[i].n,
|
|
data->sck[i].p,
|
|
data->sck[i].id, 0);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
at91sam9260_pmc->shws[data->sck[i].id] = hw;
|
|
}
|
|
|
|
for (i = 0; i < data->num_pck; i++) {
|
|
hw = at91_clk_register_peripheral(regmap,
|
|
data->pck[i].n,
|
|
"masterck_div",
|
|
data->pck[i].id);
|
|
if (IS_ERR(hw))
|
|
goto err_free;
|
|
|
|
at91sam9260_pmc->phws[data->pck[i].id] = hw;
|
|
}
|
|
|
|
of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9260_pmc);
|
|
|
|
return;
|
|
|
|
err_free:
|
|
kfree(at91sam9260_pmc);
|
|
}
|
|
|
|
static void __init at91sam9260_pmc_setup(struct device_node *np)
|
|
{
|
|
at91sam926x_pmc_setup(np, &at91sam9260_data);
|
|
}
|
|
|
|
CLK_OF_DECLARE(at91sam9260_pmc, "atmel,at91sam9260-pmc", at91sam9260_pmc_setup);
|
|
|
|
static void __init at91sam9261_pmc_setup(struct device_node *np)
|
|
{
|
|
at91sam926x_pmc_setup(np, &at91sam9261_data);
|
|
}
|
|
|
|
CLK_OF_DECLARE(at91sam9261_pmc, "atmel,at91sam9261-pmc", at91sam9261_pmc_setup);
|
|
|
|
static void __init at91sam9263_pmc_setup(struct device_node *np)
|
|
{
|
|
at91sam926x_pmc_setup(np, &at91sam9263_data);
|
|
}
|
|
|
|
CLK_OF_DECLARE(at91sam9263_pmc, "atmel,at91sam9263-pmc", at91sam9263_pmc_setup);
|
|
|
|
static void __init at91sam9g20_pmc_setup(struct device_node *np)
|
|
{
|
|
at91sam926x_pmc_setup(np, &at91sam9g20_data);
|
|
}
|
|
|
|
CLK_OF_DECLARE(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", at91sam9g20_pmc_setup);
|