163 lines
5.2 KiB
C
163 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 Collabora Ltd.
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* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt6795-clk.h>
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#include <dt-bindings/reset/mediatek,mt6795-resets.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "reset.h"
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#define GATE_PERI(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &peri_cg_regs, \
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_shift, &mtk_clk_gate_ops_setclr)
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static DEFINE_SPINLOCK(mt6795_peri_clk_lock);
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static const struct mtk_gate_regs peri_cg_regs = {
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.set_ofs = 0x0008,
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.clr_ofs = 0x0010,
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.sta_ofs = 0x0018,
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};
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static const char * const uart_ck_sel_parents[] = {
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"clk26m",
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"uart_sel",
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};
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static const struct mtk_composite peri_clks[] = {
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MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
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MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
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MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
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MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
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};
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static const struct mtk_gate peri_gates[] = {
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GATE_PERI(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
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GATE_PERI(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
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GATE_PERI(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
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GATE_PERI(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
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GATE_PERI(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
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GATE_PERI(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
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GATE_PERI(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
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GATE_PERI(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
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GATE_PERI(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
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GATE_PERI(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
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GATE_PERI(CLK_PERI_USB0, "peri_usb0", "usb30_sel", 10),
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GATE_PERI(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
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GATE_PERI(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
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GATE_PERI(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
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GATE_PERI(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
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GATE_PERI(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
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GATE_PERI(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
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GATE_PERI(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
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GATE_PERI(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
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GATE_PERI(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
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GATE_PERI(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
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GATE_PERI(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
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GATE_PERI(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
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GATE_PERI(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
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GATE_PERI(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
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GATE_PERI(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
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GATE_PERI(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
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GATE_PERI(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
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GATE_PERI(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
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GATE_PERI(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
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};
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static u16 peri_rst_ofs[] = { 0x0 };
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static u16 peri_idx_map[] = {
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[MT6795_PERI_NFI_SW_RST] = 14,
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[MT6795_PERI_THERM_SW_RST] = 16,
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[MT6795_PERI_MSDC1_SW_RST] = 20,
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};
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static const struct mtk_clk_rst_desc clk_rst_desc = {
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = peri_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(peri_rst_ofs),
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.rst_idx_map = peri_idx_map,
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.rst_idx_map_nr = ARRAY_SIZE(peri_idx_map),
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};
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static const struct of_device_id of_match_clk_mt6795_pericfg[] = {
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{ .compatible = "mediatek,mt6795-pericfg" },
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{ /* sentinel */ }
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};
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static int clk_mt6795_pericfg_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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void __iomem *base;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
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if (ret)
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goto free_clk_data;
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ret = mtk_clk_register_gates(&pdev->dev, node, peri_gates,
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ARRAY_SIZE(peri_gates), clk_data);
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if (ret)
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goto free_clk_data;
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ret = mtk_clk_register_composites(&pdev->dev, peri_clks,
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ARRAY_SIZE(peri_clks), base,
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&mt6795_peri_clk_lock, clk_data);
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if (ret)
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goto unregister_gates;
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (ret)
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goto unregister_composites;
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return 0;
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unregister_composites:
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mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data);
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unregister_gates:
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mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return ret;
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}
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static int clk_mt6795_pericfg_remove(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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of_clk_del_provider(node);
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mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data);
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mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data);
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mtk_free_clk_data(clk_data);
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return 0;
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}
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static struct platform_driver clk_mt6795_pericfg_drv = {
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.driver = {
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.name = "clk-mt6795-pericfg",
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.of_match_table = of_match_clk_mt6795_pericfg,
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},
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.probe = clk_mt6795_pericfg_probe,
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.remove = clk_mt6795_pericfg_remove,
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};
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module_platform_driver(clk_mt6795_pericfg_drv);
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MODULE_DESCRIPTION("MediaTek MT6795 pericfg clocks driver");
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MODULE_LICENSE("GPL");
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