208 lines
8.4 KiB
C
208 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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* Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
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* Author: Jianhui Zhao <zhaojh329@gmail.com>
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* Author: Daniel Golle <daniel@makrotopia.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include "clk-mux.h"
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#include <dt-bindings/clock/mediatek,mt7981-clk.h>
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#include <linux/clk.h>
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static DEFINE_SPINLOCK(mt7981_clk_lock);
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static const struct mtk_fixed_factor infra_divs[] = {
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FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
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};
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static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
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"uart_sel" };
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static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
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"spi_sel" };
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static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
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"spim_mst_sel" };
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static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
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static const char *const infra_pwm_bsel_parents[] __initconst = {
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"cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
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};
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static const char *const infra_pcie_parents[] __initconst = {
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"cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
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};
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static const struct mtk_mux infra_muxes[] = {
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/* MODULE_CLK_SEL_0 */
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
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infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
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infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
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infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
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infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
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infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
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infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
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infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
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infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
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infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
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-1, -1, -1),
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
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infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
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2, -1, -1, -1),
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/* MODULE_CLK_SEL_1 */
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MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
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infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
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-1, -1, -1),
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};
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static const struct mtk_gate_regs infra0_cg_regs = {
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.set_ofs = 0x40,
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.clr_ofs = 0x44,
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.sta_ofs = 0x48,
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};
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static const struct mtk_gate_regs infra1_cg_regs = {
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.set_ofs = 0x50,
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.clr_ofs = 0x54,
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.sta_ofs = 0x58,
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};
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static const struct mtk_gate_regs infra2_cg_regs = {
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.set_ofs = 0x60,
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.clr_ofs = 0x64,
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.sta_ofs = 0x68,
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};
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#define GATE_INFRA0(_id, _name, _parent, _shift) \
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{ \
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.id = _id, .name = _name, .parent_name = _parent, \
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.regs = &infra0_cg_regs, .shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_INFRA1(_id, _name, _parent, _shift) \
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{ \
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.id = _id, .name = _name, .parent_name = _parent, \
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.regs = &infra1_cg_regs, .shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_INFRA2(_id, _name, _parent, _shift) \
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{ \
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.id = _id, .name = _name, .parent_name = _parent, \
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.regs = &infra2_cg_regs, .shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate infra_clks[] = {
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/* INFRA0 */
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GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
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GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
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GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
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GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
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GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
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GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
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GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
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GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
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GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
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GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
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GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
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GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
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14),
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GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
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GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
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GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
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GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
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GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
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/* INFRA1 */
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GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
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GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
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GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
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GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
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GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
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GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
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GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
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GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
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GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
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GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
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GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
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GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
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GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
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13),
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GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
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14),
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GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
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GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
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GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
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GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
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GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
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GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
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GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
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GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
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GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
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GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
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/* INFRA2 */
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GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
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GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
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GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
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GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
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GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
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GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
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13),
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GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
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GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
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};
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static const struct mtk_clk_desc infracfg_desc = {
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.factor_clks = infra_divs,
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.num_factor_clks = ARRAY_SIZE(infra_divs),
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.mux_clks = infra_muxes,
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.num_mux_clks = ARRAY_SIZE(infra_muxes),
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.clks = infra_clks,
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.num_clks = ARRAY_SIZE(infra_clks),
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.clk_lock = &mt7981_clk_lock,
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};
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static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
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{ .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc },
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{ /* sentinel */ }
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};
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static struct platform_driver clk_mt7981_infracfg_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt7981-infracfg",
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.of_match_table = of_match_clk_mt7981_infracfg,
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},
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};
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builtin_platform_driver(clk_mt7981_infracfg_drv);
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