352 lines
8.5 KiB
C
352 lines
8.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019, Jeffrey Hugo
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
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#include "common.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-alpha-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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#include "reset.h"
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#include "gdsc.h"
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enum {
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P_XO,
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P_GPLL0,
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P_GPUPLL0_OUT_EVEN,
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};
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/* Instead of going directly to the block, XO is routed through this branch */
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static struct clk_branch gpucc_cxo_clk = {
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.halt_reg = 0x1020,
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.clkr = {
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.enable_reg = 0x1020,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_cxo_clk",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "xo"
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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.flags = CLK_IS_CRITICAL,
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},
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},
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};
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static struct pll_vco fabia_vco[] = {
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{ 249600000, 2000000000, 0 },
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{ 125000000, 1000000000, 1 },
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};
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static const struct clk_div_table post_div_table_fabia_even[] = {
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{ 0x0, 1 },
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{ 0x1, 2 },
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{ 0x3, 4 },
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{ 0x7, 8 },
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{ }
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};
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static struct clk_alpha_pll gpupll0 = {
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.offset = 0x0,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
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.vco_table = fabia_vco,
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.num_vco = ARRAY_SIZE(fabia_vco),
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpupll0",
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.parent_hws = (const struct clk_hw *[]){ &gpucc_cxo_clk.clkr.hw },
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.num_parents = 1,
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.ops = &clk_alpha_pll_fabia_ops,
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},
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};
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static struct clk_alpha_pll_postdiv gpupll0_out_even = {
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.offset = 0x0,
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.post_div_shift = 8,
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.post_div_table = post_div_table_fabia_even,
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.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpupll0_out_even",
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.parent_hws = (const struct clk_hw *[]){ &gpupll0.clkr.hw },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_fabia_ops,
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},
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};
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static const struct parent_map gpu_xo_gpll0_map[] = {
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{ P_XO, 0 },
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{ P_GPLL0, 5 },
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};
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static const struct clk_parent_data gpu_xo_gpll0[] = {
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{ .hw = &gpucc_cxo_clk.clkr.hw },
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{ .fw_name = "gpll0" },
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};
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static const struct parent_map gpu_xo_gpupll0_map[] = {
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{ P_XO, 0 },
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{ P_GPUPLL0_OUT_EVEN, 1 },
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};
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static const struct clk_hw *gpu_xo_gpupll0[] = {
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&gpucc_cxo_clk.clkr.hw,
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&gpupll0_out_even.clkr.hw,
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};
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static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(50000000, P_GPLL0, 12, 0, 0),
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{ }
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};
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static struct clk_rcg2 rbcpr_clk_src = {
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.cmd_rcgr = 0x1030,
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.hid_width = 5,
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.parent_map = gpu_xo_gpll0_map,
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.freq_tbl = ftbl_rbcpr_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "rbcpr_clk_src",
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.parent_data = gpu_xo_gpll0,
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.num_parents = ARRAY_SIZE(gpu_xo_gpll0),
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
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{ .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 },
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{ }
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};
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static struct clk_rcg2 gfx3d_clk_src = {
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.cmd_rcgr = 0x1070,
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.hid_width = 5,
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.parent_map = gpu_xo_gpupll0_map,
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.freq_tbl = ftbl_gfx3d_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gfx3d_clk_src",
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.parent_hws = gpu_xo_gpupll0,
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.num_parents = ARRAY_SIZE(gpu_xo_gpupll0),
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.ops = &clk_rcg2_ops,
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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},
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};
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static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 rbbmtimer_clk_src = {
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.cmd_rcgr = 0x10b0,
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.hid_width = 5,
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.parent_map = gpu_xo_gpll0_map,
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.freq_tbl = ftbl_rbbmtimer_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "rbbmtimer_clk_src",
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.parent_data = gpu_xo_gpll0,
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.num_parents = ARRAY_SIZE(gpu_xo_gpll0),
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_gfx3d_isense_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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F(40000000, P_GPLL0, 15, 0, 0),
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F(200000000, P_GPLL0, 3, 0, 0),
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F(300000000, P_GPLL0, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 gfx3d_isense_clk_src = {
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.cmd_rcgr = 0x1100,
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.hid_width = 5,
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.parent_map = gpu_xo_gpll0_map,
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.freq_tbl = ftbl_gfx3d_isense_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gfx3d_isense_clk_src",
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.parent_data = gpu_xo_gpll0,
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.num_parents = ARRAY_SIZE(gpu_xo_gpll0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch rbcpr_clk = {
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.halt_reg = 0x1054,
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.clkr = {
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.enable_reg = 0x1054,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "rbcpr_clk",
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.parent_hws = (const struct clk_hw *[]){ &rbcpr_clk_src.clkr.hw },
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_branch gfx3d_clk = {
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.halt_reg = 0x1098,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gfx3d_clk",
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.parent_hws = (const struct clk_hw *[]){ &gfx3d_clk_src.clkr.hw },
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_branch rbbmtimer_clk = {
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.halt_reg = 0x10d0,
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.clkr = {
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.enable_reg = 0x10d0,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "rbbmtimer_clk",
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.parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw },
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_branch gfx3d_isense_clk = {
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.halt_reg = 0x1124,
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.clkr = {
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.enable_reg = 0x1124,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gfx3d_isense_clk",
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.parent_hws = (const struct clk_hw *[]){ &gfx3d_isense_clk_src.clkr.hw },
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct gdsc gpu_cx_gdsc = {
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.gdscr = 0x1004,
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.gds_hw_ctrl = 0x1008,
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.pd = {
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.name = "gpu_cx",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = VOTABLE,
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};
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static struct gdsc gpu_gx_gdsc = {
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.gdscr = 0x1094,
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.clamp_io_ctrl = 0x130,
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.resets = (unsigned int []){ GPU_GX_BCR },
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.reset_count = 1,
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.cxcs = (unsigned int []){ 0x1098 },
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.cxc_count = 1,
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.pd = {
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.name = "gpu_gx",
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},
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.parent = &gpu_cx_gdsc.pd,
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.pwrsts = PWRSTS_OFF_ON | PWRSTS_RET,
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.flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
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};
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static struct clk_regmap *gpucc_msm8998_clocks[] = {
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[GPUPLL0] = &gpupll0.clkr,
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[GPUPLL0_OUT_EVEN] = &gpupll0_out_even.clkr,
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[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
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[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
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[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
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[GFX3D_ISENSE_CLK_SRC] = &gfx3d_isense_clk_src.clkr,
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[RBCPR_CLK] = &rbcpr_clk.clkr,
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[GFX3D_CLK] = &gfx3d_clk.clkr,
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[RBBMTIMER_CLK] = &rbbmtimer_clk.clkr,
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[GFX3D_ISENSE_CLK] = &gfx3d_isense_clk.clkr,
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[GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr,
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};
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static struct gdsc *gpucc_msm8998_gdscs[] = {
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[GPU_CX_GDSC] = &gpu_cx_gdsc,
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[GPU_GX_GDSC] = &gpu_gx_gdsc,
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};
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static const struct qcom_reset_map gpucc_msm8998_resets[] = {
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[GPU_CX_BCR] = { 0x1000 },
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[RBCPR_BCR] = { 0x1050 },
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[GPU_GX_BCR] = { 0x1090 },
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[GPU_ISENSE_BCR] = { 0x1120 },
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};
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static const struct regmap_config gpucc_msm8998_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x9000,
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.fast_io = true,
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};
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static const struct qcom_cc_desc gpucc_msm8998_desc = {
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.config = &gpucc_msm8998_regmap_config,
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.clks = gpucc_msm8998_clocks,
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.num_clks = ARRAY_SIZE(gpucc_msm8998_clocks),
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.resets = gpucc_msm8998_resets,
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.num_resets = ARRAY_SIZE(gpucc_msm8998_resets),
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.gdscs = gpucc_msm8998_gdscs,
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.num_gdscs = ARRAY_SIZE(gpucc_msm8998_gdscs),
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};
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static const struct of_device_id gpucc_msm8998_match_table[] = {
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{ .compatible = "qcom,msm8998-gpucc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, gpucc_msm8998_match_table);
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static int gpucc_msm8998_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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regmap = qcom_cc_map(pdev, &gpucc_msm8998_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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/* force periph logic on to avoid perf counter corruption */
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regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(13), BIT(13));
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/* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */
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regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0));
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return qcom_cc_really_probe(pdev, &gpucc_msm8998_desc, regmap);
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}
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static struct platform_driver gpucc_msm8998_driver = {
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.probe = gpucc_msm8998_probe,
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.driver = {
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.name = "gpucc-msm8998",
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.of_match_table = gpucc_msm8998_match_table,
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},
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};
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module_platform_driver(gpucc_msm8998_driver);
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MODULE_DESCRIPTION("QCOM GPUCC MSM8998 Driver");
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MODULE_LICENSE("GPL v2");
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