313 lines
12 KiB
C
313 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018-2019 SiFive, Inc.
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* Wesley Terpstra
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* Paul Walmsley
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* Zong Li
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*/
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#ifndef __SIFIVE_CLK_SIFIVE_PRCI_H
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#define __SIFIVE_CLK_SIFIVE_PRCI_H
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#include <linux/clk/analogbits-wrpll-cln28hpc.h>
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#include <linux/clk-provider.h>
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#include <linux/reset/reset-simple.h>
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#include <linux/platform_device.h>
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/*
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* EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
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* hfclk and rtcclk
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*/
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#define EXPECTED_CLK_PARENT_COUNT 2
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/*
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* Register offsets and bitmasks
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*/
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/* COREPLLCFG0 */
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#define PRCI_COREPLLCFG0_OFFSET 0x4
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#define PRCI_COREPLLCFG0_DIVR_SHIFT 0
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#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
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#define PRCI_COREPLLCFG0_DIVF_SHIFT 6
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#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
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#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
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#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
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#define PRCI_COREPLLCFG0_RANGE_SHIFT 18
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#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
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#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
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#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
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#define PRCI_COREPLLCFG0_FSE_SHIFT 25
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#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
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#define PRCI_COREPLLCFG0_LOCK_SHIFT 31
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#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
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/* COREPLLCFG1 */
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#define PRCI_COREPLLCFG1_OFFSET 0x8
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#define PRCI_COREPLLCFG1_CKE_SHIFT 31
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#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
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/* DDRPLLCFG0 */
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#define PRCI_DDRPLLCFG0_OFFSET 0xc
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#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
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#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
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#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
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#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
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#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
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#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
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#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
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#define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
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#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
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#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
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#define PRCI_DDRPLLCFG0_FSE_SHIFT 25
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#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
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#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31
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#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT)
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/* DDRPLLCFG1 */
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#define PRCI_DDRPLLCFG1_OFFSET 0x10
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#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
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#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
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/* PCIEAUX */
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#define PRCI_PCIE_AUX_OFFSET 0x14
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#define PRCI_PCIE_AUX_EN_SHIFT 0
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#define PRCI_PCIE_AUX_EN_MASK (0x1 << PRCI_PCIE_AUX_EN_SHIFT)
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/* GEMGXLPLLCFG0 */
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#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
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#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
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#define PRCI_GEMGXLPLLCFG0_DIVR_MASK (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT)
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#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6
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#define PRCI_GEMGXLPLLCFG0_DIVF_MASK (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT)
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#define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15
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#define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT)
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#define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18
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#define PRCI_GEMGXLPLLCFG0_RANGE_MASK (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT)
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#define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24
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#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT)
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#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25
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#define PRCI_GEMGXLPLLCFG0_FSE_MASK (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT)
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#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31
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#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT)
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/* GEMGXLPLLCFG1 */
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#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
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#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
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#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
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/* CORECLKSEL */
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#define PRCI_CORECLKSEL_OFFSET 0x24
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#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0
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#define PRCI_CORECLKSEL_CORECLKSEL_MASK \
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(0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT)
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/* DEVICESRESETREG */
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#define PRCI_DEVICESRESETREG_OFFSET 0x28
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#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0
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#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \
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(0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT)
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#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1
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#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \
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(0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT)
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#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2
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#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \
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(0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT)
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#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3
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#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \
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(0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
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#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5
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#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
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(0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
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#define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT 6
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#define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \
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(0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT)
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#define PRCI_RST_NR 7
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/* CLKMUXSTATUSREG */
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#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
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#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
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#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
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(0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
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/* CLTXPLLCFG0 */
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#define PRCI_CLTXPLLCFG0_OFFSET 0x30
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#define PRCI_CLTXPLLCFG0_DIVR_SHIFT 0
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#define PRCI_CLTXPLLCFG0_DIVR_MASK (0x3f << PRCI_CLTXPLLCFG0_DIVR_SHIFT)
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#define PRCI_CLTXPLLCFG0_DIVF_SHIFT 6
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#define PRCI_CLTXPLLCFG0_DIVF_MASK (0x1ff << PRCI_CLTXPLLCFG0_DIVF_SHIFT)
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#define PRCI_CLTXPLLCFG0_DIVQ_SHIFT 15
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#define PRCI_CLTXPLLCFG0_DIVQ_MASK (0x7 << PRCI_CLTXPLLCFG0_DIVQ_SHIFT)
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#define PRCI_CLTXPLLCFG0_RANGE_SHIFT 18
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#define PRCI_CLTXPLLCFG0_RANGE_MASK (0x7 << PRCI_CLTXPLLCFG0_RANGE_SHIFT)
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#define PRCI_CLTXPLLCFG0_BYPASS_SHIFT 24
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#define PRCI_CLTXPLLCFG0_BYPASS_MASK (0x1 << PRCI_CLTXPLLCFG0_BYPASS_SHIFT)
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#define PRCI_CLTXPLLCFG0_FSE_SHIFT 25
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#define PRCI_CLTXPLLCFG0_FSE_MASK (0x1 << PRCI_CLTXPLLCFG0_FSE_SHIFT)
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#define PRCI_CLTXPLLCFG0_LOCK_SHIFT 31
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#define PRCI_CLTXPLLCFG0_LOCK_MASK (0x1 << PRCI_CLTXPLLCFG0_LOCK_SHIFT)
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/* CLTXPLLCFG1 */
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#define PRCI_CLTXPLLCFG1_OFFSET 0x34
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#define PRCI_CLTXPLLCFG1_CKE_SHIFT 31
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#define PRCI_CLTXPLLCFG1_CKE_MASK (0x1 << PRCI_CLTXPLLCFG1_CKE_SHIFT)
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/* DVFSCOREPLLCFG0 */
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#define PRCI_DVFSCOREPLLCFG0_OFFSET 0x38
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/* DVFSCOREPLLCFG1 */
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#define PRCI_DVFSCOREPLLCFG1_OFFSET 0x3c
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#define PRCI_DVFSCOREPLLCFG1_CKE_SHIFT 31
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#define PRCI_DVFSCOREPLLCFG1_CKE_MASK (0x1 << PRCI_DVFSCOREPLLCFG1_CKE_SHIFT)
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/* COREPLLSEL */
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#define PRCI_COREPLLSEL_OFFSET 0x40
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#define PRCI_COREPLLSEL_COREPLLSEL_SHIFT 0
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#define PRCI_COREPLLSEL_COREPLLSEL_MASK \
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(0x1 << PRCI_COREPLLSEL_COREPLLSEL_SHIFT)
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/* HFPCLKPLLCFG0 */
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#define PRCI_HFPCLKPLLCFG0_OFFSET 0x50
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#define PRCI_HFPCLKPLL_CFG0_DIVR_SHIFT 0
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#define PRCI_HFPCLKPLL_CFG0_DIVR_MASK \
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(0x3f << PRCI_HFPCLKPLLCFG0_DIVR_SHIFT)
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#define PRCI_HFPCLKPLL_CFG0_DIVF_SHIFT 6
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#define PRCI_HFPCLKPLL_CFG0_DIVF_MASK \
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(0x1ff << PRCI_HFPCLKPLLCFG0_DIVF_SHIFT)
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#define PRCI_HFPCLKPLL_CFG0_DIVQ_SHIFT 15
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#define PRCI_HFPCLKPLL_CFG0_DIVQ_MASK \
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(0x7 << PRCI_HFPCLKPLLCFG0_DIVQ_SHIFT)
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#define PRCI_HFPCLKPLL_CFG0_RANGE_SHIFT 18
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#define PRCI_HFPCLKPLL_CFG0_RANGE_MASK \
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(0x7 << PRCI_HFPCLKPLLCFG0_RANGE_SHIFT)
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#define PRCI_HFPCLKPLL_CFG0_BYPASS_SHIFT 24
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#define PRCI_HFPCLKPLL_CFG0_BYPASS_MASK \
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(0x1 << PRCI_HFPCLKPLLCFG0_BYPASS_SHIFT)
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#define PRCI_HFPCLKPLL_CFG0_FSE_SHIFT 25
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#define PRCI_HFPCLKPLL_CFG0_FSE_MASK \
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(0x1 << PRCI_HFPCLKPLLCFG0_FSE_SHIFT)
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#define PRCI_HFPCLKPLL_CFG0_LOCK_SHIFT 31
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#define PRCI_HFPCLKPLL_CFG0_LOCK_MASK \
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(0x1 << PRCI_HFPCLKPLLCFG0_LOCK_SHIFT)
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/* HFPCLKPLLCFG1 */
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#define PRCI_HFPCLKPLLCFG1_OFFSET 0x54
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#define PRCI_HFPCLKPLLCFG1_CKE_SHIFT 31
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#define PRCI_HFPCLKPLLCFG1_CKE_MASK \
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(0x1 << PRCI_HFPCLKPLLCFG1_CKE_SHIFT)
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/* HFPCLKPLLSEL */
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#define PRCI_HFPCLKPLLSEL_OFFSET 0x58
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#define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT 0
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#define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK \
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(0x1 << PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT)
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/* HFPCLKPLLDIV */
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#define PRCI_HFPCLKPLLDIV_OFFSET 0x5c
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/* PRCIPLL */
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#define PRCI_PRCIPLL_OFFSET 0xe0
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/* PROCMONCFG */
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#define PRCI_PROCMONCFG_OFFSET 0xf0
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/*
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* Private structures
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*/
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/**
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* struct __prci_data - per-device-instance data
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* @va: base virtual address of the PRCI IP block
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* @hw_clks: encapsulates struct clk_hw records
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*
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* PRCI per-device instance data
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*/
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struct __prci_data {
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void __iomem *va;
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struct reset_simple_data reset;
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struct clk_hw_onecell_data hw_clks;
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};
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/**
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* struct __prci_wrpll_data - WRPLL configuration and integration data
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* @c: WRPLL current configuration record
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* @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
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* @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
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* @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
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* @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
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*
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* @enable_bypass and @disable_bypass are used for WRPLL instances
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* that contain a separate external glitchless clock mux downstream
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* from the PLL. The WRPLL internal bypass mux is not glitchless.
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*/
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struct __prci_wrpll_data {
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struct wrpll_cfg c;
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void (*enable_bypass)(struct __prci_data *pd);
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void (*disable_bypass)(struct __prci_data *pd);
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u8 cfg0_offs;
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u8 cfg1_offs;
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};
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/**
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* struct __prci_clock - describes a clock device managed by PRCI
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* @name: user-readable clock name string - should match the manual
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* @parent_name: parent name for this clock
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* @ops: struct clk_ops for the Linux clock framework to use for control
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* @hw: Linux-private clock data
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* @pwd: WRPLL-specific data, associated with this clock (if not NULL)
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* @pd: PRCI-specific data associated with this clock (if not NULL)
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*
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* PRCI clock data. Used by the PRCI driver to register PRCI-provided
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* clocks to the Linux clock infrastructure.
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*/
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struct __prci_clock {
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const char *name;
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const char *parent_name;
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const struct clk_ops *ops;
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struct clk_hw hw;
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struct __prci_wrpll_data *pwd;
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struct __prci_data *pd;
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};
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#define clk_hw_to_prci_clock(pwd) container_of(pwd, struct __prci_clock, hw)
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/*
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* struct prci_clk_desc - describes the information of clocks of each SoCs
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* @clks: point to a array of __prci_clock
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* @num_clks: the number of element of clks
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*/
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struct prci_clk_desc {
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struct __prci_clock *clks;
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size_t num_clks;
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};
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/* Core clock mux control */
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void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd);
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void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd);
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void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd);
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void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd);
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void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd);
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void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd);
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void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd);
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/* Linux clock framework integration */
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long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate);
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int sifive_prci_wrpll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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int sifive_clk_is_enabled(struct clk_hw *hw);
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int sifive_prci_clock_enable(struct clk_hw *hw);
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void sifive_prci_clock_disable(struct clk_hw *hw);
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unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate);
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unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate);
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unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate);
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int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw);
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int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw);
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void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw);
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#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */
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