331 lines
8.0 KiB
C
331 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include "ccu_gate.h"
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#include "ccu_mp.h"
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static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate,
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unsigned int max_m, unsigned int max_p,
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unsigned int *m, unsigned int *p)
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{
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unsigned long best_rate = 0;
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unsigned int best_m = 0, best_p = 0;
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unsigned int _m, _p;
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for (_p = 1; _p <= max_p; _p <<= 1) {
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for (_m = 1; _m <= max_m; _m++) {
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unsigned long tmp_rate = parent / _p / _m;
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if (tmp_rate > rate)
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continue;
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if ((rate - tmp_rate) < (rate - best_rate)) {
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best_rate = tmp_rate;
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best_m = _m;
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best_p = _p;
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}
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}
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}
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*m = best_m;
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*p = best_p;
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return best_rate;
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}
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static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
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unsigned long *parent,
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unsigned long rate,
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unsigned int max_m,
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unsigned int max_p)
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{
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unsigned long parent_rate_saved;
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unsigned long parent_rate, now;
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unsigned long best_rate = 0;
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unsigned int _m, _p, div;
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unsigned long maxdiv;
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parent_rate_saved = *parent;
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/*
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* The maximum divider we can use without overflowing
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* unsigned long in rate * m * p below
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*/
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maxdiv = max_m * max_p;
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maxdiv = min(ULONG_MAX / rate, maxdiv);
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for (_p = 1; _p <= max_p; _p <<= 1) {
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for (_m = 1; _m <= max_m; _m++) {
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div = _m * _p;
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if (div > maxdiv)
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break;
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if (rate * div == parent_rate_saved) {
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/*
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* It's the most ideal case if the requested
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* rate can be divided from parent clock without
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* needing to change parent rate, so return the
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* divider immediately.
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*/
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*parent = parent_rate_saved;
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return rate;
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}
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parent_rate = clk_hw_round_rate(hw, rate * div);
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now = parent_rate / div;
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if (now <= rate && now > best_rate) {
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best_rate = now;
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*parent = parent_rate;
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if (now == rate)
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return rate;
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}
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}
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}
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return best_rate;
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}
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static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
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struct clk_hw *hw,
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unsigned long *parent_rate,
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unsigned long rate,
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void *data)
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{
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struct ccu_mp *cmp = data;
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unsigned int max_m, max_p;
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unsigned int m, p;
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if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate *= cmp->fixed_post_div;
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max_m = cmp->m.max ?: 1 << cmp->m.width;
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max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
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if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {
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rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
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} else {
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rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
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max_m, max_p);
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}
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if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate /= cmp->fixed_post_div;
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return rate;
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}
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static void ccu_mp_disable(struct clk_hw *hw)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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return ccu_gate_helper_disable(&cmp->common, cmp->enable);
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}
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static int ccu_mp_enable(struct clk_hw *hw)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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return ccu_gate_helper_enable(&cmp->common, cmp->enable);
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}
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static int ccu_mp_is_enabled(struct clk_hw *hw)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable);
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}
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static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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unsigned long rate;
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unsigned int m, p;
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u32 reg;
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/* Adjust parent_rate according to pre-dividers */
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parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,
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parent_rate);
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reg = readl(cmp->common.base + cmp->common.reg);
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m = reg >> cmp->m.shift;
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m &= (1 << cmp->m.width) - 1;
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m += cmp->m.offset;
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if (!m)
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m++;
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p = reg >> cmp->p.shift;
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p &= (1 << cmp->p.width) - 1;
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rate = (parent_rate >> p) / m;
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if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate /= cmp->fixed_post_div;
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return rate;
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}
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static int ccu_mp_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux,
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req, ccu_mp_round_rate, cmp);
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}
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static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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unsigned long flags;
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unsigned int max_m, max_p;
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unsigned int m, p;
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u32 reg;
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/* Adjust parent_rate according to pre-dividers */
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parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,
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parent_rate);
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max_m = cmp->m.max ?: 1 << cmp->m.width;
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max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
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/* Adjust target rate according to post-dividers */
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if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate = rate * cmp->fixed_post_div;
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ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
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spin_lock_irqsave(cmp->common.lock, flags);
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reg = readl(cmp->common.base + cmp->common.reg);
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reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
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reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
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reg |= (m - cmp->m.offset) << cmp->m.shift;
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reg |= ilog2(p) << cmp->p.shift;
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writel(reg, cmp->common.base + cmp->common.reg);
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spin_unlock_irqrestore(cmp->common.lock, flags);
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return 0;
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}
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static u8 ccu_mp_get_parent(struct clk_hw *hw)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux);
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}
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static int ccu_mp_set_parent(struct clk_hw *hw, u8 index)
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{
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struct ccu_mp *cmp = hw_to_ccu_mp(hw);
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return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index);
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}
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const struct clk_ops ccu_mp_ops = {
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.disable = ccu_mp_disable,
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.enable = ccu_mp_enable,
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.is_enabled = ccu_mp_is_enabled,
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.get_parent = ccu_mp_get_parent,
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.set_parent = ccu_mp_set_parent,
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.determine_rate = ccu_mp_determine_rate,
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.recalc_rate = ccu_mp_recalc_rate,
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.set_rate = ccu_mp_set_rate,
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};
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EXPORT_SYMBOL_NS_GPL(ccu_mp_ops, SUNXI_CCU);
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/*
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* Support for MMC timing mode switching
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*
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* The MMC clocks on some SoCs support switching between old and
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* new timing modes. A platform specific API is provided to query
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* and set the timing mode on supported SoCs.
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*
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* In addition, a special class of ccu_mp_ops is provided, which
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* takes in to account the timing mode switch. When the new timing
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* mode is active, the clock output rate is halved. This new class
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* is a wrapper around the generic ccu_mp_ops. When clock rates
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* are passed through to ccu_mp_ops callbacks, they are doubled
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* if the new timing mode bit is set, to account for the post
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* divider. Conversely, when clock rates are passed back, they
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* are halved if the mode bit is set.
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*/
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static unsigned long ccu_mp_mmc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long rate = ccu_mp_recalc_rate(hw, parent_rate);
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struct ccu_common *cm = hw_to_ccu_common(hw);
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u32 val = readl(cm->base + cm->reg);
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if (val & CCU_MMC_NEW_TIMING_MODE)
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return rate / 2;
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return rate;
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}
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static int ccu_mp_mmc_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct ccu_common *cm = hw_to_ccu_common(hw);
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u32 val = readl(cm->base + cm->reg);
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int ret;
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/* adjust the requested clock rate */
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if (val & CCU_MMC_NEW_TIMING_MODE) {
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req->rate *= 2;
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req->min_rate *= 2;
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req->max_rate *= 2;
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}
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ret = ccu_mp_determine_rate(hw, req);
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/* re-adjust the requested clock rate back */
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if (val & CCU_MMC_NEW_TIMING_MODE) {
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req->rate /= 2;
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req->min_rate /= 2;
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req->max_rate /= 2;
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}
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return ret;
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}
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static int ccu_mp_mmc_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_common *cm = hw_to_ccu_common(hw);
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u32 val = readl(cm->base + cm->reg);
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if (val & CCU_MMC_NEW_TIMING_MODE)
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rate *= 2;
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return ccu_mp_set_rate(hw, rate, parent_rate);
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}
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const struct clk_ops ccu_mp_mmc_ops = {
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.disable = ccu_mp_disable,
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.enable = ccu_mp_enable,
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.is_enabled = ccu_mp_is_enabled,
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.get_parent = ccu_mp_get_parent,
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.set_parent = ccu_mp_set_parent,
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.determine_rate = ccu_mp_mmc_determine_rate,
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.recalc_rate = ccu_mp_mmc_recalc_rate,
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.set_rate = ccu_mp_mmc_set_rate,
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};
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EXPORT_SYMBOL_NS_GPL(ccu_mp_mmc_ops, SUNXI_CCU);
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