387 lines
9.1 KiB
C
387 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* (C) 2001 Dave Jones, Arjan van de ven.
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* (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
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*
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* Based upon reverse engineered information, and on Intel documentation
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* for chipsets ICH2-M and ICH3-M.
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*
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* Many thanks to Ducrot Bruno for finding and fixing the last
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* "missing link" for ICH2-M/ICH3-M support, and to Thomas Winkler
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* for extensive testing.
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*
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* BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
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*/
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/*********************************************************************
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* SPEEDSTEP - DEFINITIONS *
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*********************************************************************/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/pci.h>
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#include <linux/sched.h>
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#include <asm/cpu_device_id.h>
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#include "speedstep-lib.h"
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/* speedstep_chipset:
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* It is necessary to know which chipset is used. As accesses to
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* this device occur at various places in this module, we need a
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* static struct pci_dev * pointing to that device.
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*/
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static struct pci_dev *speedstep_chipset_dev;
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/* speedstep_processor
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*/
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static enum speedstep_processor speedstep_processor;
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static u32 pmbase;
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/*
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* There are only two frequency states for each processor. Values
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* are in kHz for the time being.
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*/
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static struct cpufreq_frequency_table speedstep_freqs[] = {
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{0, SPEEDSTEP_HIGH, 0},
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{0, SPEEDSTEP_LOW, 0},
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{0, 0, CPUFREQ_TABLE_END},
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};
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/**
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* speedstep_find_register - read the PMBASE address
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*
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* Returns: -ENODEV if no register could be found
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*/
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static int speedstep_find_register(void)
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{
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if (!speedstep_chipset_dev)
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return -ENODEV;
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/* get PMBASE */
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pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
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if (!(pmbase & 0x01)) {
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pr_err("could not find speedstep register\n");
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return -ENODEV;
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}
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pmbase &= 0xFFFFFFFE;
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if (!pmbase) {
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pr_err("could not find speedstep register\n");
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return -ENODEV;
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}
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pr_debug("pmbase is 0x%x\n", pmbase);
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return 0;
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}
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/**
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* speedstep_set_state - set the SpeedStep state
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* @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
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*
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* Tries to change the SpeedStep state. Can be called from
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* smp_call_function_single.
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*/
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static void speedstep_set_state(unsigned int state)
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{
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u8 pm2_blk;
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u8 value;
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unsigned long flags;
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if (state > 0x1)
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return;
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/* Disable IRQs */
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local_irq_save(flags);
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/* read state */
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value = inb(pmbase + 0x50);
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pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
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/* write new state */
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value &= 0xFE;
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value |= state;
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pr_debug("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);
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/* Disable bus master arbitration */
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pm2_blk = inb(pmbase + 0x20);
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pm2_blk |= 0x01;
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outb(pm2_blk, (pmbase + 0x20));
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/* Actual transition */
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outb(value, (pmbase + 0x50));
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/* Restore bus master arbitration */
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pm2_blk &= 0xfe;
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outb(pm2_blk, (pmbase + 0x20));
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/* check if transition was successful */
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value = inb(pmbase + 0x50);
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/* Enable IRQs */
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local_irq_restore(flags);
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pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
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if (state == (value & 0x1))
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pr_debug("change to %u MHz succeeded\n",
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speedstep_get_frequency(speedstep_processor) / 1000);
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else
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pr_err("change failed - I/O error\n");
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return;
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}
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/* Wrapper for smp_call_function_single. */
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static void _speedstep_set_state(void *_state)
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{
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speedstep_set_state(*(unsigned int *)_state);
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}
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/**
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* speedstep_activate - activate SpeedStep control in the chipset
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*
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* Tries to activate the SpeedStep status and control registers.
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* Returns -EINVAL on an unsupported chipset, and zero on success.
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*/
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static int speedstep_activate(void)
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{
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u16 value = 0;
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if (!speedstep_chipset_dev)
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return -EINVAL;
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pci_read_config_word(speedstep_chipset_dev, 0x00A0, &value);
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if (!(value & 0x08)) {
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value |= 0x08;
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pr_debug("activating SpeedStep (TM) registers\n");
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pci_write_config_word(speedstep_chipset_dev, 0x00A0, value);
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}
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return 0;
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}
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/**
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* speedstep_detect_chipset - detect the Southbridge which contains SpeedStep logic
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*
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* Detects ICH2-M, ICH3-M and ICH4-M so far. The pci_dev points to
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* the LPC bridge / PM module which contains all power-management
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* functions. Returns the SPEEDSTEP_CHIPSET_-number for the detected
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* chipset, or zero on failure.
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*/
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static unsigned int speedstep_detect_chipset(void)
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{
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speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82801DB_12,
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PCI_ANY_ID, PCI_ANY_ID,
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NULL);
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if (speedstep_chipset_dev)
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return 4; /* 4-M */
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speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82801CA_12,
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PCI_ANY_ID, PCI_ANY_ID,
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NULL);
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if (speedstep_chipset_dev)
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return 3; /* 3-M */
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speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82801BA_10,
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PCI_ANY_ID, PCI_ANY_ID,
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NULL);
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if (speedstep_chipset_dev) {
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/* speedstep.c causes lockups on Dell Inspirons 8000 and
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* 8100 which use a pretty old revision of the 82815
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* host bridge. Abort on these systems.
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*/
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struct pci_dev *hostbridge;
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hostbridge = pci_get_subsys(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82815_MC,
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PCI_ANY_ID, PCI_ANY_ID,
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NULL);
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if (!hostbridge)
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return 2; /* 2-M */
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if (hostbridge->revision < 5) {
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pr_debug("hostbridge does not support speedstep\n");
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speedstep_chipset_dev = NULL;
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pci_dev_put(hostbridge);
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return 0;
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}
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pci_dev_put(hostbridge);
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return 2; /* 2-M */
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}
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return 0;
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}
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static void get_freq_data(void *_speed)
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{
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unsigned int *speed = _speed;
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*speed = speedstep_get_frequency(speedstep_processor);
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}
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static unsigned int speedstep_get(unsigned int cpu)
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{
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unsigned int speed;
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/* You're supposed to ensure CPU is online. */
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BUG_ON(smp_call_function_single(cpu, get_freq_data, &speed, 1));
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pr_debug("detected %u kHz as current frequency\n", speed);
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return speed;
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}
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/**
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* speedstep_target - set a new CPUFreq policy
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* @policy: new policy
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* @index: index of target frequency
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*
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* Sets a new CPUFreq policy.
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*/
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static int speedstep_target(struct cpufreq_policy *policy, unsigned int index)
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{
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unsigned int policy_cpu;
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policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
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smp_call_function_single(policy_cpu, _speedstep_set_state, &index,
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true);
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return 0;
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}
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struct get_freqs {
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struct cpufreq_policy *policy;
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int ret;
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};
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static void get_freqs_on_cpu(void *_get_freqs)
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{
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struct get_freqs *get_freqs = _get_freqs;
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get_freqs->ret =
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speedstep_get_freqs(speedstep_processor,
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&speedstep_freqs[SPEEDSTEP_LOW].frequency,
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&speedstep_freqs[SPEEDSTEP_HIGH].frequency,
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&get_freqs->policy->cpuinfo.transition_latency,
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&speedstep_set_state);
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}
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static int speedstep_cpu_init(struct cpufreq_policy *policy)
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{
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unsigned int policy_cpu;
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struct get_freqs gf;
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/* only run on CPU to be set, or on its sibling */
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#ifdef CONFIG_SMP
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cpumask_copy(policy->cpus, topology_sibling_cpumask(policy->cpu));
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#endif
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policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
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/* detect low and high frequency and transition latency */
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gf.policy = policy;
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smp_call_function_single(policy_cpu, get_freqs_on_cpu, &gf, 1);
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if (gf.ret)
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return gf.ret;
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policy->freq_table = speedstep_freqs;
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return 0;
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}
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static struct cpufreq_driver speedstep_driver = {
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.name = "speedstep-ich",
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = speedstep_target,
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.init = speedstep_cpu_init,
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.get = speedstep_get,
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.attr = cpufreq_generic_attr,
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};
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static const struct x86_cpu_id ss_smi_ids[] = {
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X86_MATCH_VENDOR_FAM_MODEL(INTEL, 6, 0x8, 0),
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X86_MATCH_VENDOR_FAM_MODEL(INTEL, 6, 0xb, 0),
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X86_MATCH_VENDOR_FAM_MODEL(INTEL, 15, 0x2, 0),
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{}
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};
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/**
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* speedstep_init - initializes the SpeedStep CPUFreq driver
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*
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* Initializes the SpeedStep support. Returns -ENODEV on unsupported
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* devices, -EINVAL on problems during initiatization, and zero on
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* success.
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*/
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static int __init speedstep_init(void)
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{
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if (!x86_match_cpu(ss_smi_ids))
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return -ENODEV;
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/* detect processor */
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speedstep_processor = speedstep_detect_processor();
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if (!speedstep_processor) {
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pr_debug("Intel(R) SpeedStep(TM) capable processor "
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"not found\n");
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return -ENODEV;
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}
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/* detect chipset */
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if (!speedstep_detect_chipset()) {
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pr_debug("Intel(R) SpeedStep(TM) for this chipset not "
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"(yet) available.\n");
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return -ENODEV;
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}
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/* activate speedstep support */
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if (speedstep_activate()) {
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pci_dev_put(speedstep_chipset_dev);
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return -EINVAL;
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}
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if (speedstep_find_register())
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return -ENODEV;
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return cpufreq_register_driver(&speedstep_driver);
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}
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/**
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* speedstep_exit - unregisters SpeedStep support
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*
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* Unregisters SpeedStep support.
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*/
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static void __exit speedstep_exit(void)
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{
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pci_dev_put(speedstep_chipset_dev);
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cpufreq_unregister_driver(&speedstep_driver);
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}
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MODULE_AUTHOR("Dave Jones, Dominik Brodowski <linux@brodo.de>");
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MODULE_DESCRIPTION("Speedstep driver for Intel mobile processors on chipsets "
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"with ICH-M southbridges.");
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MODULE_LICENSE("GPL");
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module_init(speedstep_init);
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module_exit(speedstep_exit);
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