410 lines
12 KiB
C
410 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Driver for the Synopsys DesignWare AHB DMA Controller
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*
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* Copyright (C) 2005-2007 Atmel Corporation
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* Copyright (C) 2010-2011 ST Microelectronics
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* Copyright (C) 2016 Intel Corporation
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*/
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/io-64-nonatomic-hi-lo.h>
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#include "internal.h"
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#define DW_DMA_MAX_NR_REQUESTS 16
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/* flow controller */
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enum dw_dma_fc {
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DW_DMA_FC_D_M2M,
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DW_DMA_FC_D_M2P,
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DW_DMA_FC_D_P2M,
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DW_DMA_FC_D_P2P,
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DW_DMA_FC_P_P2M,
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DW_DMA_FC_SP_P2P,
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DW_DMA_FC_P_M2P,
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DW_DMA_FC_DP_P2P,
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};
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/*
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* Redefine this macro to handle differences between 32- and 64-bit
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* addressing, big vs. little endian, etc.
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*/
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#define DW_REG(name) u32 name; u32 __pad_##name
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/* Hardware register definitions. */
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struct dw_dma_chan_regs {
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DW_REG(SAR); /* Source Address Register */
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DW_REG(DAR); /* Destination Address Register */
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DW_REG(LLP); /* Linked List Pointer */
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u32 CTL_LO; /* Control Register Low */
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u32 CTL_HI; /* Control Register High */
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DW_REG(SSTAT);
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DW_REG(DSTAT);
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DW_REG(SSTATAR);
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DW_REG(DSTATAR);
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u32 CFG_LO; /* Configuration Register Low */
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u32 CFG_HI; /* Configuration Register High */
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DW_REG(SGR);
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DW_REG(DSR);
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};
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struct dw_dma_irq_regs {
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DW_REG(XFER);
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DW_REG(BLOCK);
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DW_REG(SRC_TRAN);
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DW_REG(DST_TRAN);
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DW_REG(ERROR);
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};
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struct dw_dma_regs {
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/* per-channel registers */
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struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
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/* irq handling */
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struct dw_dma_irq_regs RAW; /* r */
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struct dw_dma_irq_regs STATUS; /* r (raw & mask) */
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struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */
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struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */
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DW_REG(STATUS_INT); /* r */
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/* software handshaking */
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DW_REG(REQ_SRC);
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DW_REG(REQ_DST);
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DW_REG(SGL_REQ_SRC);
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DW_REG(SGL_REQ_DST);
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DW_REG(LAST_SRC);
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DW_REG(LAST_DST);
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/* miscellaneous */
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DW_REG(CFG);
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DW_REG(CH_EN);
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DW_REG(ID);
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DW_REG(TEST);
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/* iDMA 32-bit support */
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DW_REG(CLASS_PRIORITY0);
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DW_REG(CLASS_PRIORITY1);
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/* optional encoded params, 0x3c8..0x3f7 */
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u32 __reserved;
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/* per-channel configuration registers */
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u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
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u32 MULTI_BLK_TYPE;
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u32 MAX_BLK_SIZE;
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/* top-level parameters */
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u32 DW_PARAMS;
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/* component ID */
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u32 COMP_TYPE;
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u32 COMP_VERSION;
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/* iDMA 32-bit support */
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DW_REG(FIFO_PARTITION0);
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DW_REG(FIFO_PARTITION1);
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DW_REG(SAI_ERR);
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DW_REG(GLOBAL_CFG);
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};
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/* Bitfields in DW_PARAMS */
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#define DW_PARAMS_NR_CHAN 8 /* number of channels */
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#define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */
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#define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
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#define DW_PARAMS_DATA_WIDTH1 15 /* master 1 data width */
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#define DW_PARAMS_DATA_WIDTH2 17 /* master 2 data width */
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#define DW_PARAMS_DATA_WIDTH3 19 /* master 3 data width */
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#define DW_PARAMS_DATA_WIDTH4 21 /* master 4 data width */
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#define DW_PARAMS_EN 28 /* encoded parameters */
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/* Bitfields in DWC_PARAMS */
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#define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */
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#define DWC_PARAMS_HC_LLP 13 /* set LLP register to zero */
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#define DWC_PARAMS_MSIZE 16 /* max group transaction size */
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/* bursts size */
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enum dw_dma_msize {
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DW_DMA_MSIZE_1,
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DW_DMA_MSIZE_4,
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DW_DMA_MSIZE_8,
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DW_DMA_MSIZE_16,
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DW_DMA_MSIZE_32,
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DW_DMA_MSIZE_64,
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DW_DMA_MSIZE_128,
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DW_DMA_MSIZE_256,
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};
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/* Bitfields in LLP */
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#define DWC_LLP_LMS(x) ((x) & 3) /* list master select */
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#define DWC_LLP_LOC(x) ((x) & ~3) /* next lli */
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/* Bitfields in CTL_LO */
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#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
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#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
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#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
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#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
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#define DWC_CTLL_DST_DEC (1<<7)
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#define DWC_CTLL_DST_FIX (2<<7)
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#define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */
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#define DWC_CTLL_SRC_DEC (1<<9)
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#define DWC_CTLL_SRC_FIX (2<<9)
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#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
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#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
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#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
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#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
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#define DWC_CTLL_FC(n) ((n) << 20)
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#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
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#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
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#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
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#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */
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/* plus 4 transfer types for peripheral-as-flow-controller */
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#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */
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#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */
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#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
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#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
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/* Bitfields in CTL_HI */
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#define DWC_CTLH_BLOCK_TS_MASK GENMASK(11, 0)
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#define DWC_CTLH_BLOCK_TS(x) ((x) & DWC_CTLH_BLOCK_TS_MASK)
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#define DWC_CTLH_DONE (1 << 12)
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/* Bitfields in CFG_LO */
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#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
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#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
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#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
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#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
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#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
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#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */
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#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
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#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
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#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
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#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
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#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
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#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
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#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
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#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
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#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
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#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
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#define DWC_CFGL_MAX_BURST(x) ((x) << 20)
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#define DWC_CFGL_RELOAD_SAR (1 << 30)
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#define DWC_CFGL_RELOAD_DAR (1 << 31)
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/* Bitfields in CFG_HI */
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#define DWC_CFGH_FCMODE (1 << 0)
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#define DWC_CFGH_FIFO_MODE (1 << 1)
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#define DWC_CFGH_PROTCTL(x) ((x) << 2)
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#define DWC_CFGH_PROTCTL_DATA (0 << 2) /* data access - always set */
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#define DWC_CFGH_PROTCTL_PRIV (1 << 2) /* privileged -> AHB HPROT[1] */
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#define DWC_CFGH_PROTCTL_BUFFER (2 << 2) /* bufferable -> AHB HPROT[2] */
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#define DWC_CFGH_PROTCTL_CACHE (4 << 2) /* cacheable -> AHB HPROT[3] */
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#define DWC_CFGH_DS_UPD_EN (1 << 5)
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#define DWC_CFGH_SS_UPD_EN (1 << 6)
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#define DWC_CFGH_SRC_PER(x) ((x) << 7)
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#define DWC_CFGH_DST_PER(x) ((x) << 11)
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/* Bitfields in SGR */
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#define DWC_SGR_SGI(x) ((x) << 0)
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#define DWC_SGR_SGC(x) ((x) << 20)
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/* Bitfields in DSR */
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#define DWC_DSR_DSI(x) ((x) << 0)
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#define DWC_DSR_DSC(x) ((x) << 20)
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/* Bitfields in CFG */
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#define DW_CFG_DMA_EN (1 << 0)
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/* iDMA 32-bit support */
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/* bursts size */
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enum idma32_msize {
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IDMA32_MSIZE_1,
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IDMA32_MSIZE_2,
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IDMA32_MSIZE_4,
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IDMA32_MSIZE_8,
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IDMA32_MSIZE_16,
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IDMA32_MSIZE_32,
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};
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/* Bitfields in CTL_HI */
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#define IDMA32C_CTLH_BLOCK_TS_MASK GENMASK(16, 0)
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#define IDMA32C_CTLH_BLOCK_TS(x) ((x) & IDMA32C_CTLH_BLOCK_TS_MASK)
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#define IDMA32C_CTLH_DONE (1 << 17)
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/* Bitfields in CFG_LO */
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#define IDMA32C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */
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#define IDMA32C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */
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#define IDMA32C_CFGL_CH_DRAIN (1 << 10) /* drain FIFO */
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#define IDMA32C_CFGL_DST_OPT_BL (1 << 20) /* optimize dst burst length */
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#define IDMA32C_CFGL_SRC_OPT_BL (1 << 21) /* optimize src burst length */
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/* Bitfields in CFG_HI */
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#define IDMA32C_CFGH_SRC_PER(x) ((x) << 0)
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#define IDMA32C_CFGH_DST_PER(x) ((x) << 4)
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#define IDMA32C_CFGH_RD_ISSUE_THD(x) ((x) << 8)
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#define IDMA32C_CFGH_RW_ISSUE_THD(x) ((x) << 18)
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#define IDMA32C_CFGH_SRC_PER_EXT(x) ((x) << 28) /* src peripheral extension */
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#define IDMA32C_CFGH_DST_PER_EXT(x) ((x) << 30) /* dst peripheral extension */
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/* Bitfields in FIFO_PARTITION */
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#define IDMA32C_FP_PSIZE_CH0(x) ((x) << 0)
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#define IDMA32C_FP_PSIZE_CH1(x) ((x) << 13)
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#define IDMA32C_FP_UPDATE (1 << 26)
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enum dw_dmac_flags {
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DW_DMA_IS_CYCLIC = 0,
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DW_DMA_IS_SOFT_LLP = 1,
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DW_DMA_IS_PAUSED = 2,
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DW_DMA_IS_INITIALIZED = 3,
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};
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struct dw_dma_chan {
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struct dma_chan chan;
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void __iomem *ch_regs;
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u8 mask;
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u8 priority;
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enum dma_transfer_direction direction;
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/* software emulation of the LLP transfers */
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struct list_head *tx_node_active;
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spinlock_t lock;
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/* these other elements are all protected by lock */
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unsigned long flags;
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struct list_head active_list;
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struct list_head queue;
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unsigned int descs_allocated;
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/* hardware configuration */
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unsigned int block_size;
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bool nollp;
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u32 max_burst;
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/* custom slave configuration */
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struct dw_dma_slave dws;
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/* configuration passed via .device_config */
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struct dma_slave_config dma_sconfig;
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};
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static inline struct dw_dma_chan_regs __iomem *
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__dwc_regs(struct dw_dma_chan *dwc)
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{
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return dwc->ch_regs;
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}
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#define channel_readl(dwc, name) \
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readl(&(__dwc_regs(dwc)->name))
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#define channel_writel(dwc, name, val) \
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writel((val), &(__dwc_regs(dwc)->name))
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static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
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{
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return container_of(chan, struct dw_dma_chan, chan);
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}
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struct dw_dma {
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struct dma_device dma;
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char name[20];
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void __iomem *regs;
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struct dma_pool *desc_pool;
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struct tasklet_struct tasklet;
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/* channels */
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struct dw_dma_chan *chan;
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u8 all_chan_mask;
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u8 in_use;
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/* Channel operations */
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void (*initialize_chan)(struct dw_dma_chan *dwc);
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void (*suspend_chan)(struct dw_dma_chan *dwc, bool drain);
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void (*resume_chan)(struct dw_dma_chan *dwc, bool drain);
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u32 (*prepare_ctllo)(struct dw_dma_chan *dwc);
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void (*encode_maxburst)(struct dw_dma_chan *dwc, u32 *maxburst);
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u32 (*bytes2block)(struct dw_dma_chan *dwc, size_t bytes,
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unsigned int width, size_t *len);
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size_t (*block2bytes)(struct dw_dma_chan *dwc, u32 block, u32 width);
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/* Device operations */
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void (*set_device_name)(struct dw_dma *dw, int id);
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void (*disable)(struct dw_dma *dw);
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void (*enable)(struct dw_dma *dw);
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/* platform data */
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struct dw_dma_platform_data *pdata;
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};
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static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
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{
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return dw->regs;
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}
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#define dma_readl(dw, name) \
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readl(&(__dw_regs(dw)->name))
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#define dma_writel(dw, name, val) \
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writel((val), &(__dw_regs(dw)->name))
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#define idma32_readq(dw, name) \
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hi_lo_readq(&(__dw_regs(dw)->name))
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#define idma32_writeq(dw, name, val) \
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hi_lo_writeq((val), &(__dw_regs(dw)->name))
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#define channel_set_bit(dw, reg, mask) \
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dma_writel(dw, reg, ((mask) << 8) | (mask))
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#define channel_clear_bit(dw, reg, mask) \
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dma_writel(dw, reg, ((mask) << 8) | 0)
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static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
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{
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return container_of(ddev, struct dw_dma, dma);
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}
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/* LLI == Linked List Item; a.k.a. DMA block descriptor */
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struct dw_lli {
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/* values that are not changed by hardware */
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__le32 sar;
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__le32 dar;
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__le32 llp; /* chain to next lli */
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__le32 ctllo;
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/* values that may get written back: */
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__le32 ctlhi;
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/* sstat and dstat can snapshot peripheral register state.
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* silicon config may discard either or both...
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*/
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__le32 sstat;
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__le32 dstat;
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};
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struct dw_desc {
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/* FIRST values the hardware uses */
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struct dw_lli lli;
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#define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_le32(v))
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#define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_le32(v))
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#define lli_read(d, reg) le32_to_cpu((d)->lli.reg)
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#define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_le32(v))
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/* THEN values for driver housekeeping */
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struct list_head desc_node;
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struct list_head tx_list;
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struct dma_async_tx_descriptor txd;
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size_t len;
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size_t total_len;
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u32 residue;
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};
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#define to_dw_desc(h) list_entry(h, struct dw_desc, desc_node)
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static inline struct dw_desc *
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txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
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{
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return container_of(txd, struct dw_desc, txd);
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}
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