332 lines
8.1 KiB
C
332 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel I/OAT DMA Linux driver
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* Copyright(c) 2007 - 2009 Intel Corporation.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/dca.h>
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/* either a kernel change is needed, or we need something like this in kernel */
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#ifndef CONFIG_SMP
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#include <asm/smp.h>
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#undef cpu_physical_id
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#define cpu_physical_id(cpu) (cpuid_ebx(1) >> 24)
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#endif
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#include "dma.h"
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#include "registers.h"
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/*
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* Bit 7 of a tag map entry is the "valid" bit, if it is set then bits 0:6
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* contain the bit number of the APIC ID to map into the DCA tag. If the valid
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* bit is not set, then the value must be 0 or 1 and defines the bit in the tag.
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*/
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#define DCA_TAG_MAP_VALID 0x80
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#define DCA3_TAG_MAP_BIT_TO_INV 0x80
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#define DCA3_TAG_MAP_BIT_TO_SEL 0x40
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#define DCA3_TAG_MAP_LITERAL_VAL 0x1
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#define DCA_TAG_MAP_MASK 0xDF
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/* expected tag map bytes for I/OAT ver.2 */
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#define DCA2_TAG_MAP_BYTE0 0x80
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#define DCA2_TAG_MAP_BYTE1 0x0
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#define DCA2_TAG_MAP_BYTE2 0x81
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#define DCA2_TAG_MAP_BYTE3 0x82
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#define DCA2_TAG_MAP_BYTE4 0x82
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/*
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* "Legacy" DCA systems do not implement the DCA register set in the
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* I/OAT device. Software needs direct support for their tag mappings.
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*/
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#define APICID_BIT(x) (DCA_TAG_MAP_VALID | (x))
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#define IOAT_TAG_MAP_LEN 8
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/* pack PCI B/D/F into a u16 */
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static inline u16 dcaid_from_pcidev(struct pci_dev *pci)
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{
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return (pci->bus->number << 8) | pci->devfn;
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}
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static int dca_enabled_in_bios(struct pci_dev *pdev)
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{
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/* CPUID level 9 returns DCA configuration */
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/* Bit 0 indicates DCA enabled by the BIOS */
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unsigned long cpuid_level_9;
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int res;
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cpuid_level_9 = cpuid_eax(9);
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res = test_bit(0, &cpuid_level_9);
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if (!res)
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dev_dbg(&pdev->dev, "DCA is disabled in BIOS\n");
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return res;
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}
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int system_has_dca_enabled(struct pci_dev *pdev)
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{
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if (boot_cpu_has(X86_FEATURE_DCA))
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return dca_enabled_in_bios(pdev);
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dev_dbg(&pdev->dev, "boot cpu doesn't have X86_FEATURE_DCA\n");
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return 0;
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}
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struct ioat_dca_slot {
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struct pci_dev *pdev; /* requester device */
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u16 rid; /* requester id, as used by IOAT */
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};
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#define IOAT_DCA_MAX_REQ 6
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#define IOAT3_DCA_MAX_REQ 2
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struct ioat_dca_priv {
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void __iomem *iobase;
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void __iomem *dca_base;
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int max_requesters;
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int requester_count;
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u8 tag_map[IOAT_TAG_MAP_LEN];
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struct ioat_dca_slot req_slots[];
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};
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static int ioat_dca_dev_managed(struct dca_provider *dca,
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struct device *dev)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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struct pci_dev *pdev;
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int i;
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pdev = to_pci_dev(dev);
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for (i = 0; i < ioatdca->max_requesters; i++) {
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if (ioatdca->req_slots[i].pdev == pdev)
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return 1;
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}
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return 0;
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}
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static int ioat_dca_add_requester(struct dca_provider *dca, struct device *dev)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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struct pci_dev *pdev;
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int i;
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u16 id;
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u16 global_req_table;
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/* This implementation only supports PCI-Express */
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if (!dev_is_pci(dev))
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return -ENODEV;
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pdev = to_pci_dev(dev);
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id = dcaid_from_pcidev(pdev);
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if (ioatdca->requester_count == ioatdca->max_requesters)
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return -ENODEV;
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for (i = 0; i < ioatdca->max_requesters; i++) {
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if (ioatdca->req_slots[i].pdev == NULL) {
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/* found an empty slot */
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ioatdca->requester_count++;
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ioatdca->req_slots[i].pdev = pdev;
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ioatdca->req_slots[i].rid = id;
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global_req_table =
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readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);
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writel(id | IOAT_DCA_GREQID_VALID,
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ioatdca->iobase + global_req_table + (i * 4));
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return i;
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}
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}
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/* Error, ioatdma->requester_count is out of whack */
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return -EFAULT;
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}
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static int ioat_dca_remove_requester(struct dca_provider *dca,
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struct device *dev)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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struct pci_dev *pdev;
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int i;
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u16 global_req_table;
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/* This implementation only supports PCI-Express */
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if (!dev_is_pci(dev))
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return -ENODEV;
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pdev = to_pci_dev(dev);
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for (i = 0; i < ioatdca->max_requesters; i++) {
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if (ioatdca->req_slots[i].pdev == pdev) {
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global_req_table =
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readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);
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writel(0, ioatdca->iobase + global_req_table + (i * 4));
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ioatdca->req_slots[i].pdev = NULL;
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ioatdca->req_slots[i].rid = 0;
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ioatdca->requester_count--;
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return i;
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}
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}
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return -ENODEV;
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}
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static u8 ioat_dca_get_tag(struct dca_provider *dca,
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struct device *dev,
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int cpu)
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{
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u8 tag;
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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int i, apic_id, bit, value;
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u8 entry;
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tag = 0;
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apic_id = cpu_physical_id(cpu);
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for (i = 0; i < IOAT_TAG_MAP_LEN; i++) {
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entry = ioatdca->tag_map[i];
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if (entry & DCA3_TAG_MAP_BIT_TO_SEL) {
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bit = entry &
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~(DCA3_TAG_MAP_BIT_TO_SEL | DCA3_TAG_MAP_BIT_TO_INV);
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value = (apic_id & (1 << bit)) ? 1 : 0;
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} else if (entry & DCA3_TAG_MAP_BIT_TO_INV) {
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bit = entry & ~DCA3_TAG_MAP_BIT_TO_INV;
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value = (apic_id & (1 << bit)) ? 0 : 1;
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} else {
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value = (entry & DCA3_TAG_MAP_LITERAL_VAL) ? 1 : 0;
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}
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tag |= (value << i);
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}
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return tag;
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}
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static const struct dca_ops ioat_dca_ops = {
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.add_requester = ioat_dca_add_requester,
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.remove_requester = ioat_dca_remove_requester,
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.get_tag = ioat_dca_get_tag,
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.dev_managed = ioat_dca_dev_managed,
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};
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static int ioat_dca_count_dca_slots(void *iobase, u16 dca_offset)
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{
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int slots = 0;
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u32 req;
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u16 global_req_table;
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global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET);
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if (global_req_table == 0)
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return 0;
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do {
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req = readl(iobase + global_req_table + (slots * sizeof(u32)));
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slots++;
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} while ((req & IOAT_DCA_GREQID_LASTID) == 0);
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return slots;
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}
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static inline int dca3_tag_map_invalid(u8 *tag_map)
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{
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/*
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* If the tag map is not programmed by the BIOS the default is:
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* 0x80 0x80 0x80 0x80 0x80 0x00 0x00 0x00
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*
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* This an invalid map and will result in only 2 possible tags
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* 0x1F and 0x00. 0x00 is an invalid DCA tag so we know that
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* this entire definition is invalid.
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*/
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return ((tag_map[0] == DCA_TAG_MAP_VALID) &&
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(tag_map[1] == DCA_TAG_MAP_VALID) &&
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(tag_map[2] == DCA_TAG_MAP_VALID) &&
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(tag_map[3] == DCA_TAG_MAP_VALID) &&
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(tag_map[4] == DCA_TAG_MAP_VALID));
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}
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struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase)
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{
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struct dca_provider *dca;
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struct ioat_dca_priv *ioatdca;
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int slots;
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int i;
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int err;
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u16 dca_offset;
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u16 csi_fsb_control;
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u16 pcie_control;
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u8 bit;
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union {
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u64 full;
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struct {
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u32 low;
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u32 high;
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};
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} tag_map;
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if (!system_has_dca_enabled(pdev))
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return NULL;
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dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET);
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if (dca_offset == 0)
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return NULL;
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slots = ioat_dca_count_dca_slots(iobase, dca_offset);
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if (slots == 0)
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return NULL;
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dca = alloc_dca_provider(&ioat_dca_ops,
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struct_size(ioatdca, req_slots, slots));
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if (!dca)
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return NULL;
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ioatdca = dca_priv(dca);
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ioatdca->iobase = iobase;
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ioatdca->dca_base = iobase + dca_offset;
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ioatdca->max_requesters = slots;
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/* some bios might not know to turn these on */
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csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);
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if ((csi_fsb_control & IOAT3_CSI_CONTROL_PREFETCH) == 0) {
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csi_fsb_control |= IOAT3_CSI_CONTROL_PREFETCH;
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writew(csi_fsb_control,
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ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);
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}
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pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);
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if ((pcie_control & IOAT3_PCI_CONTROL_MEMWR) == 0) {
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pcie_control |= IOAT3_PCI_CONTROL_MEMWR;
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writew(pcie_control,
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ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);
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}
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/* TODO version, compatibility and configuration checks */
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/* copy out the APIC to DCA tag map */
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tag_map.low =
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readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_LOW);
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tag_map.high =
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readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_HIGH);
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for (i = 0; i < 8; i++) {
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bit = tag_map.full >> (8 * i);
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ioatdca->tag_map[i] = bit & DCA_TAG_MAP_MASK;
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}
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if (dca3_tag_map_invalid(ioatdca->tag_map)) {
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add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
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pr_warn_once("%s %s: APICID_TAG_MAP set incorrectly by BIOS, disabling DCA\n",
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dev_driver_string(&pdev->dev),
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dev_name(&pdev->dev));
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free_dca_provider(dca);
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return NULL;
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}
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err = register_dca_provider(dca, &pdev->dev);
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if (err) {
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free_dca_provider(dca);
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return NULL;
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}
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return dca;
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}
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