83 lines
2.6 KiB
C
83 lines
2.6 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __MXGPU_NV_H__
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#define __MXGPU_NV_H__
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#define NV_MAILBOX_POLL_ACK_TIMEDOUT 500
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#define NV_MAILBOX_POLL_MSG_TIMEDOUT 6000
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#define NV_MAILBOX_POLL_FLR_TIMEDOUT 5000
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#define NV_MAILBOX_POLL_MSG_REP_MAX 11
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enum idh_request {
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IDH_REQ_GPU_INIT_ACCESS = 1,
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IDH_REL_GPU_INIT_ACCESS,
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IDH_REQ_GPU_FINI_ACCESS,
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IDH_REL_GPU_FINI_ACCESS,
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IDH_REQ_GPU_RESET_ACCESS,
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IDH_REQ_GPU_INIT_DATA,
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IDH_LOG_VF_ERROR = 200,
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IDH_READY_TO_RESET = 201,
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IDH_RAS_POISON = 202,
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};
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enum idh_event {
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IDH_CLR_MSG_BUF = 0,
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IDH_READY_TO_ACCESS_GPU,
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IDH_FLR_NOTIFICATION,
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IDH_FLR_NOTIFICATION_CMPL,
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IDH_SUCCESS,
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IDH_FAIL,
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IDH_QUERY_ALIVE,
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IDH_REQ_GPU_INIT_DATA_READY,
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IDH_TEXT_MESSAGE = 255,
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};
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extern const struct amdgpu_virt_ops xgpu_nv_virt_ops;
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void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev);
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int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev);
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int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev);
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void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev);
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#define mmMAILBOX_CONTROL 0xE5E
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#define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (mmMAILBOX_CONTROL * 4)
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#define NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE (NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE + 1)
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#define mmMAILBOX_MSGBUF_TRN_DW0 0xE56
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#define mmMAILBOX_MSGBUF_TRN_DW1 0xE57
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#define mmMAILBOX_MSGBUF_TRN_DW2 0xE58
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#define mmMAILBOX_MSGBUF_TRN_DW3 0xE59
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#define mmMAILBOX_MSGBUF_RCV_DW0 0xE5A
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#define mmMAILBOX_MSGBUF_RCV_DW1 0xE5B
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#define mmMAILBOX_MSGBUF_RCV_DW2 0xE5C
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#define mmMAILBOX_MSGBUF_RCV_DW3 0xE5D
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#define mmMAILBOX_INT_CNTL 0xE5F
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#endif
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