1098 lines
29 KiB
C
1098 lines
29 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include "dce_audio.h"
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#include "dce/dce_11_0_d.h"
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#include "dce/dce_11_0_sh_mask.h"
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#define DCE_AUD(audio)\
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container_of(audio, struct dce_audio, base)
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#define CTX \
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aud->base.ctx
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#define DC_LOGGER_INIT()
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#define REG(reg)\
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(aud->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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aud->shifts->field_name, aud->masks->field_name
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#define IX_REG(reg)\
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ix ## reg
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#define AZ_REG_READ(reg_name) \
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read_indirect_azalia_reg(audio, IX_REG(reg_name))
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#define AZ_REG_WRITE(reg_name, value) \
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write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
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static void write_indirect_azalia_reg(struct audio *audio,
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uint32_t reg_index,
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uint32_t reg_data)
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{
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struct dce_audio *aud = DCE_AUD(audio);
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/* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
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REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
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AZALIA_ENDPOINT_REG_INDEX, reg_index);
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/* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
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REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
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AZALIA_ENDPOINT_REG_DATA, reg_data);
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}
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static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
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{
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struct dce_audio *aud = DCE_AUD(audio);
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uint32_t value = 0;
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/* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
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REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
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AZALIA_ENDPOINT_REG_INDEX, reg_index);
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/* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
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value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
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return value;
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}
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static bool is_audio_format_supported(
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const struct audio_info *audio_info,
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enum audio_format_code audio_format_code,
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uint32_t *format_index)
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{
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uint32_t index;
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uint32_t max_channe_index = 0;
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bool found = false;
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if (audio_info == NULL)
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return found;
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/* pass through whole array */
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for (index = 0; index < audio_info->mode_count; index++) {
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if (audio_info->modes[index].format_code == audio_format_code) {
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if (found) {
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/* format has multiply entries, choose one with
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* highst number of channels */
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if (audio_info->modes[index].channel_count >
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audio_info->modes[max_channe_index].channel_count) {
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max_channe_index = index;
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}
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} else {
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/* format found, save it's index */
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found = true;
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max_channe_index = index;
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}
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}
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}
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/* return index */
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if (found && format_index != NULL)
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*format_index = max_channe_index;
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return found;
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}
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/*For HDMI, calculate if specified sample rates can fit into a given timing */
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static void check_audio_bandwidth_hdmi(
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const struct audio_crtc_info *crtc_info,
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uint32_t channel_count,
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union audio_sample_rates *sample_rates)
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{
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uint32_t samples;
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uint32_t h_blank;
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bool limit_freq_to_48_khz = false;
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bool limit_freq_to_88_2_khz = false;
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bool limit_freq_to_96_khz = false;
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bool limit_freq_to_174_4_khz = false;
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if (!crtc_info)
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return;
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/* For two channels supported return whatever sink support,unmodified*/
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if (channel_count > 2) {
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/* Based on HDMI spec 1.3 Table 7.5 */
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if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
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(crtc_info->v_active <= 576) &&
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!(crtc_info->interlaced) &&
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!(crtc_info->pixel_repetition == 2 ||
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crtc_info->pixel_repetition == 4)) {
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limit_freq_to_48_khz = true;
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} else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
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(crtc_info->v_active <= 576) &&
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(crtc_info->interlaced) &&
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(crtc_info->pixel_repetition == 2)) {
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limit_freq_to_88_2_khz = true;
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} else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) &&
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(crtc_info->v_active <= 576) &&
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!(crtc_info->interlaced)) {
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limit_freq_to_174_4_khz = true;
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}
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}
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/* Also do some calculation for the available Audio Bandwidth for the
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* 8 ch (i.e. for the Layout 1 => ch > 2)
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*/
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h_blank = crtc_info->h_total - crtc_info->h_active;
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if (crtc_info->pixel_repetition)
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h_blank *= crtc_info->pixel_repetition;
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/*based on HDMI spec 1.3 Table 7.5 */
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h_blank -= 58;
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/*for Control Period */
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h_blank -= 16;
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samples = h_blank * 10;
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/* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
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* of Audio samples per line multiplied by 10 - Layout 1)
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*/
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samples /= 32;
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samples *= crtc_info->v_active;
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/*Number of samples multiplied by 10, per second */
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samples *= crtc_info->refresh_rate;
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/*Number of Audio samples per second */
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samples /= 10;
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/* @todo do it after deep color is implemented
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* 8xx - deep color bandwidth scaling
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* Extra bandwidth is avaliable in deep color b/c link runs faster than
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* pixel rate. This has the effect of allowing more tmds characters to
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* be transmitted during blank
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*/
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switch (crtc_info->color_depth) {
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case COLOR_DEPTH_888:
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samples *= 4;
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break;
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case COLOR_DEPTH_101010:
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samples *= 5;
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break;
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case COLOR_DEPTH_121212:
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samples *= 6;
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break;
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default:
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samples *= 4;
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break;
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}
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samples /= 4;
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/*check limitation*/
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if (samples < 88200)
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limit_freq_to_48_khz = true;
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else if (samples < 96000)
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limit_freq_to_88_2_khz = true;
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else if (samples < 176400)
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limit_freq_to_96_khz = true;
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else if (samples < 192000)
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limit_freq_to_174_4_khz = true;
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if (sample_rates != NULL) {
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/* limit frequencies */
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if (limit_freq_to_174_4_khz)
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sample_rates->rate.RATE_192 = 0;
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if (limit_freq_to_96_khz) {
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sample_rates->rate.RATE_192 = 0;
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sample_rates->rate.RATE_176_4 = 0;
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}
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if (limit_freq_to_88_2_khz) {
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sample_rates->rate.RATE_192 = 0;
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sample_rates->rate.RATE_176_4 = 0;
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sample_rates->rate.RATE_96 = 0;
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}
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if (limit_freq_to_48_khz) {
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sample_rates->rate.RATE_192 = 0;
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sample_rates->rate.RATE_176_4 = 0;
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sample_rates->rate.RATE_96 = 0;
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sample_rates->rate.RATE_88_2 = 0;
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}
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}
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}
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/*For DP SST, calculate if specified sample rates can fit into a given timing */
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static void check_audio_bandwidth_dpsst(
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const struct audio_crtc_info *crtc_info,
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uint32_t channel_count,
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union audio_sample_rates *sample_rates)
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{
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/* do nothing */
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}
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/*For DP MST, calculate if specified sample rates can fit into a given timing */
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static void check_audio_bandwidth_dpmst(
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const struct audio_crtc_info *crtc_info,
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uint32_t channel_count,
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union audio_sample_rates *sample_rates)
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{
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/* do nothing */
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}
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static void check_audio_bandwidth(
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const struct audio_crtc_info *crtc_info,
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uint32_t channel_count,
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enum signal_type signal,
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union audio_sample_rates *sample_rates)
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{
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switch (signal) {
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case SIGNAL_TYPE_HDMI_TYPE_A:
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check_audio_bandwidth_hdmi(
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crtc_info, channel_count, sample_rates);
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break;
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case SIGNAL_TYPE_EDP:
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case SIGNAL_TYPE_DISPLAY_PORT:
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check_audio_bandwidth_dpsst(
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crtc_info, channel_count, sample_rates);
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break;
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case SIGNAL_TYPE_DISPLAY_PORT_MST:
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check_audio_bandwidth_dpmst(
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crtc_info, channel_count, sample_rates);
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break;
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default:
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break;
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}
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}
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/* expose/not expose HBR capability to Audio driver */
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static void set_high_bit_rate_capable(
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struct audio *audio,
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bool capable)
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{
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uint32_t value = 0;
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/* set high bit rate audio capable*/
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value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
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set_reg_field_value(value, capable,
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AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
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HBR_CAPABLE);
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AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value);
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}
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/* set video latency in ms/2+1 */
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static void set_video_latency(
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struct audio *audio,
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int latency_in_ms)
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{
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uint32_t value = 0;
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if ((latency_in_ms < 0) || (latency_in_ms > 255))
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return;
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value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
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set_reg_field_value(value, latency_in_ms,
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AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
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VIDEO_LIPSYNC);
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AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
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value);
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}
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/* set audio latency in ms/2+1 */
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static void set_audio_latency(
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struct audio *audio,
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int latency_in_ms)
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{
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uint32_t value = 0;
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if (latency_in_ms < 0)
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latency_in_ms = 0;
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if (latency_in_ms > 255)
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latency_in_ms = 255;
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value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
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set_reg_field_value(value, latency_in_ms,
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AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
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AUDIO_LIPSYNC);
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AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
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value);
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}
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void dce_aud_az_enable(struct audio *audio)
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{
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uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
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DC_LOGGER_INIT();
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set_reg_field_value(value, 1,
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AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
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CLOCK_GATING_DISABLE);
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set_reg_field_value(value, 1,
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AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
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AUDIO_ENABLED);
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AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
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set_reg_field_value(value, 0,
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AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
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CLOCK_GATING_DISABLE);
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AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
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DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n",
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audio->inst, value);
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}
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void dce_aud_az_disable(struct audio *audio)
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{
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uint32_t value;
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DC_LOGGER_INIT();
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value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
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set_reg_field_value(value, 1,
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AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
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CLOCK_GATING_DISABLE);
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AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
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set_reg_field_value(value, 0,
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AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
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AUDIO_ENABLED);
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AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
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set_reg_field_value(value, 0,
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AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
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CLOCK_GATING_DISABLE);
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AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
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value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
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DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n",
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audio->inst, value);
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}
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void dce_aud_az_configure(
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struct audio *audio,
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enum signal_type signal,
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const struct audio_crtc_info *crtc_info,
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const struct audio_info *audio_info)
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{
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struct dce_audio *aud = DCE_AUD(audio);
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uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
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uint32_t value;
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uint32_t field = 0;
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enum audio_format_code audio_format_code;
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uint32_t format_index;
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uint32_t index;
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bool is_ac3_supported = false;
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union audio_sample_rates sample_rate;
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uint32_t strlen = 0;
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value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
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set_reg_field_value(value, 1,
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AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
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CLOCK_GATING_DISABLE);
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AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
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/* Speaker Allocation */
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/*
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uint32_t value;
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uint32_t field = 0;*/
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value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
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set_reg_field_value(value,
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speakers,
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AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
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SPEAKER_ALLOCATION);
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/* LFE_PLAYBACK_LEVEL = LFEPBL
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* LFEPBL = 0 : Unknown or refer to other information
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* LFEPBL = 1 : 0dB playback
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* LFEPBL = 2 : +10dB playback
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* LFE_BL = 3 : Reserved
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*/
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set_reg_field_value(value,
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0,
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AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
|
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LFE_PLAYBACK_LEVEL);
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/* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only.
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* why are we writing to it? DCE8 does not write this */
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|
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set_reg_field_value(value,
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0,
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AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
|
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HDMI_CONNECTION);
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|
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set_reg_field_value(value,
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0,
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AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
|
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DP_CONNECTION);
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field = get_reg_field_value(value,
|
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AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
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EXTRA_CONNECTION_INFO);
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field &= ~0x1;
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set_reg_field_value(value,
|
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field,
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AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
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EXTRA_CONNECTION_INFO);
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|
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/* set audio for output signal */
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switch (signal) {
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case SIGNAL_TYPE_HDMI_TYPE_A:
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set_reg_field_value(value,
|
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1,
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AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
|
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HDMI_CONNECTION);
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|
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break;
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case SIGNAL_TYPE_EDP:
|
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case SIGNAL_TYPE_DISPLAY_PORT:
|
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case SIGNAL_TYPE_DISPLAY_PORT_MST:
|
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set_reg_field_value(value,
|
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1,
|
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AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
|
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DP_CONNECTION);
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break;
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default:
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BREAK_TO_DEBUGGER();
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break;
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}
|
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|
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AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value);
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|
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/* ACP Data - Supports AI */
|
|
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA);
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|
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set_reg_field_value(
|
|
value,
|
|
audio_info->flags.info.SUPPORT_AI,
|
|
AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA,
|
|
SUPPORTS_AI);
|
|
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, value);
|
|
|
|
/* Audio Descriptors */
|
|
/* pass through all formats */
|
|
for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
|
|
format_index++) {
|
|
audio_format_code =
|
|
(AUDIO_FORMAT_CODE_FIRST + format_index);
|
|
|
|
/* those are unsupported, skip programming */
|
|
if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
|
|
audio_format_code == AUDIO_FORMAT_CODE_DST)
|
|
continue;
|
|
|
|
value = 0;
|
|
|
|
/* check if supported */
|
|
if (is_audio_format_supported(
|
|
audio_info, audio_format_code, &index)) {
|
|
const struct audio_mode *audio_mode =
|
|
&audio_info->modes[index];
|
|
union audio_sample_rates sample_rates =
|
|
audio_mode->sample_rates;
|
|
uint8_t byte2 = audio_mode->max_bit_rate;
|
|
uint8_t channel_count = audio_mode->channel_count;
|
|
|
|
/* adjust specific properties */
|
|
switch (audio_format_code) {
|
|
case AUDIO_FORMAT_CODE_LINEARPCM: {
|
|
|
|
check_audio_bandwidth(
|
|
crtc_info,
|
|
channel_count,
|
|
signal,
|
|
&sample_rates);
|
|
|
|
byte2 = audio_mode->sample_size;
|
|
|
|
set_reg_field_value(value,
|
|
sample_rates.all,
|
|
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
|
|
SUPPORTED_FREQUENCIES_STEREO);
|
|
}
|
|
break;
|
|
case AUDIO_FORMAT_CODE_AC3:
|
|
is_ac3_supported = true;
|
|
break;
|
|
case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
|
|
case AUDIO_FORMAT_CODE_DTS_HD:
|
|
case AUDIO_FORMAT_CODE_MAT_MLP:
|
|
case AUDIO_FORMAT_CODE_DST:
|
|
case AUDIO_FORMAT_CODE_WMAPRO:
|
|
byte2 = audio_mode->vendor_specific;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* fill audio format data */
|
|
set_reg_field_value(value,
|
|
channel_count - 1,
|
|
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
|
|
MAX_CHANNELS);
|
|
|
|
set_reg_field_value(value,
|
|
sample_rates.all,
|
|
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
|
|
SUPPORTED_FREQUENCIES);
|
|
|
|
set_reg_field_value(value,
|
|
byte2,
|
|
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
|
|
DESCRIPTOR_BYTE_2);
|
|
} /* if */
|
|
|
|
AZ_REG_WRITE(
|
|
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index,
|
|
value);
|
|
} /* for */
|
|
|
|
if (is_ac3_supported)
|
|
/* todo: this reg global. why program global register? */
|
|
REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
|
|
0x05);
|
|
|
|
/* check for 192khz/8-Ch support for HBR requirements */
|
|
sample_rate.all = 0;
|
|
sample_rate.rate.RATE_192 = 1;
|
|
|
|
check_audio_bandwidth(
|
|
crtc_info,
|
|
8,
|
|
signal,
|
|
&sample_rate);
|
|
|
|
set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192);
|
|
|
|
/* Audio and Video Lipsync */
|
|
set_video_latency(audio, audio_info->video_latency);
|
|
set_audio_latency(audio, audio_info->audio_latency);
|
|
|
|
value = 0;
|
|
set_reg_field_value(value, audio_info->manufacture_id,
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
|
|
MANUFACTURER_ID);
|
|
|
|
set_reg_field_value(value, audio_info->product_id,
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
|
|
PRODUCT_ID);
|
|
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
|
|
value);
|
|
|
|
value = 0;
|
|
|
|
/*get display name string length */
|
|
while (audio_info->display_name[strlen++] != '\0') {
|
|
if (strlen >=
|
|
MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
|
|
break;
|
|
}
|
|
set_reg_field_value(value, strlen,
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
|
|
SINK_DESCRIPTION_LEN);
|
|
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
|
|
value);
|
|
DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n",
|
|
audio->inst, value, audio_info->display_name);
|
|
|
|
/*
|
|
*write the port ID:
|
|
*PORT_ID0 = display index
|
|
*PORT_ID1 = 16bit BDF
|
|
*(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
|
|
*/
|
|
|
|
value = 0;
|
|
|
|
set_reg_field_value(value, audio_info->port_id[0],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
|
|
PORT_ID0);
|
|
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value);
|
|
|
|
value = 0;
|
|
set_reg_field_value(value, audio_info->port_id[1],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
|
|
PORT_ID1);
|
|
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value);
|
|
|
|
/*write the 18 char monitor string */
|
|
|
|
value = 0;
|
|
set_reg_field_value(value, audio_info->display_name[0],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
|
|
DESCRIPTION0);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[1],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
|
|
DESCRIPTION1);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[2],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
|
|
DESCRIPTION2);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[3],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
|
|
DESCRIPTION3);
|
|
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value);
|
|
|
|
value = 0;
|
|
set_reg_field_value(value, audio_info->display_name[4],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
|
|
DESCRIPTION4);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[5],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
|
|
DESCRIPTION5);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[6],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
|
|
DESCRIPTION6);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[7],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
|
|
DESCRIPTION7);
|
|
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value);
|
|
|
|
value = 0;
|
|
set_reg_field_value(value, audio_info->display_name[8],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
|
|
DESCRIPTION8);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[9],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
|
|
DESCRIPTION9);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[10],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
|
|
DESCRIPTION10);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[11],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
|
|
DESCRIPTION11);
|
|
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value);
|
|
|
|
value = 0;
|
|
set_reg_field_value(value, audio_info->display_name[12],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
|
|
DESCRIPTION12);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[13],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
|
|
DESCRIPTION13);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[14],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
|
|
DESCRIPTION14);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[15],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
|
|
DESCRIPTION15);
|
|
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value);
|
|
|
|
value = 0;
|
|
set_reg_field_value(value, audio_info->display_name[16],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
|
|
DESCRIPTION16);
|
|
|
|
set_reg_field_value(value, audio_info->display_name[17],
|
|
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
|
|
DESCRIPTION17);
|
|
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value);
|
|
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
|
|
set_reg_field_value(value, 0,
|
|
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
|
|
CLOCK_GATING_DISABLE);
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
|
|
}
|
|
|
|
/*
|
|
* todo: wall clk related functionality probably belong to clock_src.
|
|
*/
|
|
|
|
/* search pixel clock value for Azalia HDMI Audio */
|
|
static void get_azalia_clock_info_hdmi(
|
|
uint32_t crtc_pixel_clock_100hz,
|
|
uint32_t actual_pixel_clock_100Hz,
|
|
struct azalia_clock_info *azalia_clock_info)
|
|
{
|
|
/* audio_dto_phase= 24 * 10,000;
|
|
* 24MHz in [100Hz] units */
|
|
azalia_clock_info->audio_dto_phase =
|
|
24 * 10000;
|
|
|
|
/* audio_dto_module = PCLKFrequency * 10,000;
|
|
* [khz] -> [100Hz] */
|
|
azalia_clock_info->audio_dto_module =
|
|
actual_pixel_clock_100Hz;
|
|
}
|
|
|
|
static void get_azalia_clock_info_dp(
|
|
uint32_t requested_pixel_clock_100Hz,
|
|
const struct audio_pll_info *pll_info,
|
|
struct azalia_clock_info *azalia_clock_info)
|
|
{
|
|
/* Reported dpDtoSourceClockInkhz value for
|
|
* DCE8 already adjusted for SS, do not need any
|
|
* adjustment here anymore
|
|
*/
|
|
|
|
/*audio_dto_phase = 24 * 10,000;
|
|
* 24MHz in [100Hz] units */
|
|
azalia_clock_info->audio_dto_phase = 24 * 10000;
|
|
|
|
/*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
|
|
* [khz] ->[100Hz] */
|
|
azalia_clock_info->audio_dto_module =
|
|
pll_info->dp_dto_source_clock_in_khz * 10;
|
|
}
|
|
|
|
void dce_aud_wall_dto_setup(
|
|
struct audio *audio,
|
|
enum signal_type signal,
|
|
const struct audio_crtc_info *crtc_info,
|
|
const struct audio_pll_info *pll_info)
|
|
{
|
|
struct dce_audio *aud = DCE_AUD(audio);
|
|
|
|
struct azalia_clock_info clock_info = { 0 };
|
|
|
|
if (dc_is_hdmi_tmds_signal(signal)) {
|
|
uint32_t src_sel;
|
|
|
|
/*DTO0 Programming goal:
|
|
-generate 24MHz, 128*Fs from 24MHz
|
|
-use DTO0 when an active HDMI port is connected
|
|
(optionally a DP is connected) */
|
|
|
|
/* calculate DTO settings */
|
|
get_azalia_clock_info_hdmi(
|
|
crtc_info->requested_pixel_clock_100Hz,
|
|
crtc_info->calculated_pixel_clock_100Hz,
|
|
&clock_info);
|
|
|
|
DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
|
|
"calculated_pixel_clock_100Hz =%d\n"\
|
|
"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
|
|
crtc_info->requested_pixel_clock_100Hz,\
|
|
crtc_info->calculated_pixel_clock_100Hz,\
|
|
clock_info.audio_dto_module,\
|
|
clock_info.audio_dto_phase);
|
|
|
|
/* On TN/SI, Program DTO source select and DTO select before
|
|
programming DTO modulo and DTO phase. These bits must be
|
|
programmed first, otherwise there will be no HDMI audio at boot
|
|
up. This is a HW sequence change (different from old ASICs).
|
|
Caution when changing this programming sequence.
|
|
|
|
HDMI enabled, using DTO0
|
|
program master CRTC for DTO0 */
|
|
src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
|
|
REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
|
|
DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
|
|
DCCG_AUDIO_DTO_SEL, 0);
|
|
|
|
/* module */
|
|
REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
|
|
DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
|
|
|
|
/* phase */
|
|
REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
|
|
DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
|
|
} else {
|
|
/*DTO1 Programming goal:
|
|
-generate 24MHz, 512*Fs, 128*Fs from 24MHz
|
|
-default is to used DTO1, and switch to DTO0 when an audio
|
|
master HDMI port is connected
|
|
-use as default for DP
|
|
|
|
calculate DTO settings */
|
|
get_azalia_clock_info_dp(
|
|
crtc_info->requested_pixel_clock_100Hz,
|
|
pll_info,
|
|
&clock_info);
|
|
|
|
/* Program DTO select before programming DTO modulo and DTO
|
|
phase. default to use DTO1 */
|
|
|
|
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
|
|
DCCG_AUDIO_DTO_SEL, 1);
|
|
|
|
/* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
|
|
* Select 512fs for DP TODO: web register definition
|
|
* does not match register header file
|
|
* DCE11 version it's commented out while DCE8 it's set to 1
|
|
*/
|
|
|
|
/* module */
|
|
REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
|
|
DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
|
|
|
|
/* phase */
|
|
REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
|
|
DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
|
|
|
|
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
|
|
DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);
|
|
|
|
}
|
|
}
|
|
|
|
#if defined(CONFIG_DRM_AMD_DC_SI)
|
|
static void dce60_aud_wall_dto_setup(
|
|
struct audio *audio,
|
|
enum signal_type signal,
|
|
const struct audio_crtc_info *crtc_info,
|
|
const struct audio_pll_info *pll_info)
|
|
{
|
|
struct dce_audio *aud = DCE_AUD(audio);
|
|
|
|
struct azalia_clock_info clock_info = { 0 };
|
|
|
|
if (dc_is_hdmi_signal(signal)) {
|
|
uint32_t src_sel;
|
|
|
|
/*DTO0 Programming goal:
|
|
-generate 24MHz, 128*Fs from 24MHz
|
|
-use DTO0 when an active HDMI port is connected
|
|
(optionally a DP is connected) */
|
|
|
|
/* calculate DTO settings */
|
|
get_azalia_clock_info_hdmi(
|
|
crtc_info->requested_pixel_clock_100Hz,
|
|
crtc_info->calculated_pixel_clock_100Hz,
|
|
&clock_info);
|
|
|
|
DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
|
|
"calculated_pixel_clock_100Hz =%d\n"\
|
|
"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
|
|
crtc_info->requested_pixel_clock_100Hz,\
|
|
crtc_info->calculated_pixel_clock_100Hz,\
|
|
clock_info.audio_dto_module,\
|
|
clock_info.audio_dto_phase);
|
|
|
|
/* On TN/SI, Program DTO source select and DTO select before
|
|
programming DTO modulo and DTO phase. These bits must be
|
|
programmed first, otherwise there will be no HDMI audio at boot
|
|
up. This is a HW sequence change (different from old ASICs).
|
|
Caution when changing this programming sequence.
|
|
|
|
HDMI enabled, using DTO0
|
|
program master CRTC for DTO0 */
|
|
src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
|
|
REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
|
|
DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
|
|
DCCG_AUDIO_DTO_SEL, 0);
|
|
|
|
/* module */
|
|
REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
|
|
DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
|
|
|
|
/* phase */
|
|
REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
|
|
DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
|
|
} else {
|
|
/*DTO1 Programming goal:
|
|
-generate 24MHz, 128*Fs from 24MHz (DCE6 does not support 512*Fs)
|
|
-default is to used DTO1, and switch to DTO0 when an audio
|
|
master HDMI port is connected
|
|
-use as default for DP
|
|
|
|
calculate DTO settings */
|
|
get_azalia_clock_info_dp(
|
|
crtc_info->requested_pixel_clock_100Hz,
|
|
pll_info,
|
|
&clock_info);
|
|
|
|
/* Program DTO select before programming DTO modulo and DTO
|
|
phase. default to use DTO1 */
|
|
|
|
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
|
|
DCCG_AUDIO_DTO_SEL, 1);
|
|
|
|
/* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
|
|
* Cannot select 512fs for DP
|
|
*
|
|
* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask
|
|
*/
|
|
|
|
/* module */
|
|
REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
|
|
DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
|
|
|
|
/* phase */
|
|
REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
|
|
DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
|
|
|
|
/* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE reg */
|
|
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static bool dce_aud_endpoint_valid(struct audio *audio)
|
|
{
|
|
uint32_t value;
|
|
uint32_t port_connectivity;
|
|
|
|
value = AZ_REG_READ(
|
|
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
|
|
|
|
port_connectivity = get_reg_field_value(value,
|
|
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
|
|
PORT_CONNECTIVITY);
|
|
|
|
return !(port_connectivity == 1);
|
|
}
|
|
|
|
/* initialize HW state */
|
|
void dce_aud_hw_init(
|
|
struct audio *audio)
|
|
{
|
|
uint32_t value;
|
|
struct dce_audio *aud = DCE_AUD(audio);
|
|
|
|
/* we only need to program the following registers once, so we only do
|
|
it for the inst 0*/
|
|
if (audio->inst != 0)
|
|
return;
|
|
|
|
/* Suport R5 - 32khz
|
|
* Suport R6 - 44.1khz
|
|
* Suport R7 - 48khz
|
|
*/
|
|
/*disable clock gating before write to endpoint register*/
|
|
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
|
|
set_reg_field_value(value, 1,
|
|
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
|
|
CLOCK_GATING_DISABLE);
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
|
|
REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
|
|
AUDIO_RATE_CAPABILITIES, 0x70);
|
|
|
|
/*Keep alive bit to verify HW block in BU. */
|
|
REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
|
|
CLKSTOP, 1,
|
|
EPSS, 1);
|
|
set_reg_field_value(value, 0,
|
|
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
|
|
CLOCK_GATING_DISABLE);
|
|
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
|
|
}
|
|
|
|
static const struct audio_funcs funcs = {
|
|
.endpoint_valid = dce_aud_endpoint_valid,
|
|
.hw_init = dce_aud_hw_init,
|
|
.wall_dto_setup = dce_aud_wall_dto_setup,
|
|
.az_enable = dce_aud_az_enable,
|
|
.az_disable = dce_aud_az_disable,
|
|
.az_configure = dce_aud_az_configure,
|
|
.destroy = dce_aud_destroy,
|
|
};
|
|
|
|
#if defined(CONFIG_DRM_AMD_DC_SI)
|
|
static const struct audio_funcs dce60_funcs = {
|
|
.endpoint_valid = dce_aud_endpoint_valid,
|
|
.hw_init = dce_aud_hw_init,
|
|
.wall_dto_setup = dce60_aud_wall_dto_setup,
|
|
.az_enable = dce_aud_az_enable,
|
|
.az_disable = dce_aud_az_disable,
|
|
.az_configure = dce_aud_az_configure,
|
|
.destroy = dce_aud_destroy,
|
|
};
|
|
#endif
|
|
|
|
void dce_aud_destroy(struct audio **audio)
|
|
{
|
|
struct dce_audio *aud = DCE_AUD(*audio);
|
|
|
|
kfree(aud);
|
|
*audio = NULL;
|
|
}
|
|
|
|
struct audio *dce_audio_create(
|
|
struct dc_context *ctx,
|
|
unsigned int inst,
|
|
const struct dce_audio_registers *reg,
|
|
const struct dce_audio_shift *shifts,
|
|
const struct dce_audio_mask *masks
|
|
)
|
|
{
|
|
struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
|
|
|
|
if (audio == NULL) {
|
|
ASSERT_CRITICAL(audio);
|
|
return NULL;
|
|
}
|
|
|
|
audio->base.ctx = ctx;
|
|
audio->base.inst = inst;
|
|
audio->base.funcs = &funcs;
|
|
|
|
audio->regs = reg;
|
|
audio->shifts = shifts;
|
|
audio->masks = masks;
|
|
return &audio->base;
|
|
}
|
|
|
|
#if defined(CONFIG_DRM_AMD_DC_SI)
|
|
struct audio *dce60_audio_create(
|
|
struct dc_context *ctx,
|
|
unsigned int inst,
|
|
const struct dce_audio_registers *reg,
|
|
const struct dce_audio_shift *shifts,
|
|
const struct dce_audio_mask *masks
|
|
)
|
|
{
|
|
struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
|
|
|
|
if (audio == NULL) {
|
|
ASSERT_CRITICAL(audio);
|
|
return NULL;
|
|
}
|
|
|
|
audio->base.ctx = ctx;
|
|
audio->base.inst = inst;
|
|
audio->base.funcs = &dce60_funcs;
|
|
|
|
audio->regs = reg;
|
|
audio->shifts = shifts;
|
|
audio->masks = masks;
|
|
return &audio->base;
|
|
}
|
|
#endif
|