509 lines
16 KiB
C
509 lines
16 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dmub_psr.h"
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#include "dc.h"
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#include "dc_dmub_srv.h"
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#include "dmub/dmub_srv.h"
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#include "core_types.h"
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#define DC_TRACE_LEVEL_MESSAGE(...) do {} while (0) /* do nothing */
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#define MAX_PIPES 6
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/*
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* Convert dmcub psr state to dmcu psr state.
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*/
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static enum dc_psr_state convert_psr_state(uint32_t raw_state)
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{
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enum dc_psr_state state = PSR_STATE0;
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if (raw_state == 0)
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state = PSR_STATE0;
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else if (raw_state == 0x10)
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state = PSR_STATE1;
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else if (raw_state == 0x11)
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state = PSR_STATE1a;
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else if (raw_state == 0x20)
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state = PSR_STATE2;
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else if (raw_state == 0x21)
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state = PSR_STATE2a;
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else if (raw_state == 0x22)
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state = PSR_STATE2b;
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else if (raw_state == 0x30)
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state = PSR_STATE3;
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else if (raw_state == 0x31)
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state = PSR_STATE3Init;
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else if (raw_state == 0x40)
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state = PSR_STATE4;
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else if (raw_state == 0x41)
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state = PSR_STATE4a;
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else if (raw_state == 0x42)
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state = PSR_STATE4b;
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else if (raw_state == 0x43)
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state = PSR_STATE4c;
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else if (raw_state == 0x44)
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state = PSR_STATE4d;
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else if (raw_state == 0x50)
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state = PSR_STATE5;
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else if (raw_state == 0x51)
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state = PSR_STATE5a;
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else if (raw_state == 0x52)
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state = PSR_STATE5b;
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else if (raw_state == 0x53)
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state = PSR_STATE5c;
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else if (raw_state == 0x4A)
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state = PSR_STATE4_FULL_FRAME;
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else if (raw_state == 0x4B)
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state = PSR_STATE4a_FULL_FRAME;
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else if (raw_state == 0x4C)
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state = PSR_STATE4b_FULL_FRAME;
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else if (raw_state == 0x4D)
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state = PSR_STATE4c_FULL_FRAME;
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else if (raw_state == 0x4E)
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state = PSR_STATE4_FULL_FRAME_POWERUP;
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else if (raw_state == 0x60)
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state = PSR_STATE_HWLOCK_MGR;
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else if (raw_state == 0x61)
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state = PSR_STATE_POLLVUPDATE;
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else
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state = PSR_STATE_INVALID;
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return state;
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}
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/*
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* Get PSR state from firmware.
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*/
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static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst)
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{
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struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
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uint32_t raw_state = 0;
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uint32_t retry_count = 0;
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enum dmub_status status;
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do {
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// Send gpint command and wait for ack
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status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, panel_inst, 30);
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if (status == DMUB_STATUS_OK) {
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// GPINT was executed, get response
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dmub_srv_get_gpint_response(srv, &raw_state);
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*state = convert_psr_state(raw_state);
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} else
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// Return invalid state when GPINT times out
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*state = PSR_STATE_INVALID;
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} while (++retry_count <= 1000 && *state == PSR_STATE_INVALID);
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// Assert if max retry hit
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if (retry_count >= 1000 && *state == PSR_STATE_INVALID) {
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ASSERT(0);
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DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
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WPP_BIT_FLAG_Firmware_PsrState,
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"Unable to get PSR state from FW.");
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} else
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DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
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WPP_BIT_FLAG_Firmware_PsrState,
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"Got PSR state from FW. PSR state: %d, Retry count: %d",
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*state, retry_count);
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}
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/*
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* Set PSR version.
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*/
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static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst)
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{
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union dmub_rb_cmd cmd;
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struct dc_context *dc = dmub->ctx;
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if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)
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return false;
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memset(&cmd, 0, sizeof(cmd));
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cmd.psr_set_version.header.type = DMUB_CMD__PSR;
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cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION;
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switch (stream->link->psr_settings.psr_version) {
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case DC_PSR_VERSION_1:
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cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1;
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break;
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case DC_PSR_VERSION_SU_1:
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cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_SU_1;
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break;
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case DC_PSR_VERSION_UNSUPPORTED:
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default:
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cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED;
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break;
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}
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if (cmd.psr_set_version.psr_set_version_data.version == PSR_VERSION_UNSUPPORTED)
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return false;
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cmd.psr_set_version.psr_set_version_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
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cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst;
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cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data);
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dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
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dc_dmub_srv_cmd_execute(dc->dmub_srv);
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dc_dmub_srv_wait_idle(dc->dmub_srv);
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return true;
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}
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/*
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* Enable/Disable PSR.
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*/
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static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst)
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{
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union dmub_rb_cmd cmd;
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struct dc_context *dc = dmub->ctx;
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uint32_t retry_count;
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enum dc_psr_state state = PSR_STATE0;
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memset(&cmd, 0, sizeof(cmd));
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cmd.psr_enable.header.type = DMUB_CMD__PSR;
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cmd.psr_enable.data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
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cmd.psr_enable.data.panel_inst = panel_inst;
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if (enable)
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cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE;
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else
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cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_DISABLE;
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cmd.psr_enable.header.payload_bytes = 0; // Send header only
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dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
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dc_dmub_srv_cmd_execute(dc->dmub_srv);
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dc_dmub_srv_wait_idle(dc->dmub_srv);
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/* Below loops 1000 x 500us = 500 ms.
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* Exit PSR may need to wait 1-2 frames to power up. Timeout after at
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* least a few frames. Should never hit the max retry assert below.
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*/
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if (wait) {
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for (retry_count = 0; retry_count <= 1000; retry_count++) {
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dmub_psr_get_state(dmub, &state, panel_inst);
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if (enable) {
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if (state != PSR_STATE0)
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break;
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} else {
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if (state == PSR_STATE0)
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break;
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}
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udelay(500);
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}
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/* assert if max retry hit */
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if (retry_count >= 1000)
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ASSERT(0);
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}
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}
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/*
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* Set PSR level.
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*/
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static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst)
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{
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union dmub_rb_cmd cmd;
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enum dc_psr_state state = PSR_STATE0;
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struct dc_context *dc = dmub->ctx;
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dmub_psr_get_state(dmub, &state, panel_inst);
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if (state == PSR_STATE0)
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return;
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memset(&cmd, 0, sizeof(cmd));
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cmd.psr_set_level.header.type = DMUB_CMD__PSR;
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cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL;
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cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data);
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cmd.psr_set_level.psr_set_level_data.psr_level = psr_level;
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cmd.psr_set_level.psr_set_level_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
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cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst;
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dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
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dc_dmub_srv_cmd_execute(dc->dmub_srv);
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dc_dmub_srv_wait_idle(dc->dmub_srv);
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}
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/**
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* Set PSR vtotal requirement for FreeSync PSR.
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*/
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static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub,
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uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
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{
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union dmub_rb_cmd cmd;
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struct dc_context *dc = dmub->ctx;
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memset(&cmd, 0, sizeof(cmd));
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cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR;
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cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE;
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cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data);
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cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle;
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cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su;
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dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
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dc_dmub_srv_cmd_execute(dc->dmub_srv);
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dc_dmub_srv_wait_idle(dc->dmub_srv);
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}
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/*
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* Set PSR power optimization flags.
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*/
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static void dmub_psr_set_power_opt(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst)
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{
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union dmub_rb_cmd cmd;
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struct dc_context *dc = dmub->ctx;
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memset(&cmd, 0, sizeof(cmd));
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cmd.psr_set_power_opt.header.type = DMUB_CMD__PSR;
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cmd.psr_set_power_opt.header.sub_type = DMUB_CMD__SET_PSR_POWER_OPT;
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cmd.psr_set_power_opt.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_power_opt_data);
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cmd.psr_set_power_opt.psr_set_power_opt_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
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cmd.psr_set_power_opt.psr_set_power_opt_data.power_opt = power_opt;
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cmd.psr_set_power_opt.psr_set_power_opt_data.panel_inst = panel_inst;
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dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
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dc_dmub_srv_cmd_execute(dc->dmub_srv);
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dc_dmub_srv_wait_idle(dc->dmub_srv);
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}
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/*
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* Setup PSR by programming phy registers and sending psr hw context values to firmware.
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*/
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static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
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struct dc_link *link,
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struct psr_context *psr_context,
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uint8_t panel_inst)
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{
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union dmub_rb_cmd cmd;
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struct dc_context *dc = dmub->ctx;
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struct dmub_cmd_psr_copy_settings_data *copy_settings_data
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= &cmd.psr_copy_settings.psr_copy_settings_data;
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struct pipe_ctx *pipe_ctx = NULL;
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struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
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int i = 0;
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for (i = 0; i < MAX_PIPES; i++) {
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if (res_ctx->pipe_ctx[i].stream &&
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res_ctx->pipe_ctx[i].stream->link == link &&
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res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
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pipe_ctx = &res_ctx->pipe_ctx[i];
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//TODO: refactor for multi edp support
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break;
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}
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}
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if (!pipe_ctx)
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return false;
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// First, set the psr version
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if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst))
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return false;
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// Program DP DPHY fast training registers
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link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
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psr_context->psrExitLinkTrainingRequired);
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// Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high
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link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
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psr_context->sdpTransmitLineNumDeadline);
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memset(&cmd, 0, sizeof(cmd));
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cmd.psr_copy_settings.header.type = DMUB_CMD__PSR;
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cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS;
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cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data);
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// Hw insts
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copy_settings_data->dpphy_inst = psr_context->transmitterId;
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copy_settings_data->aux_inst = psr_context->channel;
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copy_settings_data->digfe_inst = psr_context->engineId;
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copy_settings_data->digbe_inst = psr_context->transmitterId;
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copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
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if (pipe_ctx->plane_res.dpp)
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copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
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else
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copy_settings_data->dpp_inst = 0;
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if (pipe_ctx->stream_res.opp)
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copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst;
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else
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copy_settings_data->opp_inst = 0;
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if (pipe_ctx->stream_res.tg)
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copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;
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else
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copy_settings_data->otg_inst = 0;
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// Misc
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copy_settings_data->use_phy_fsm = link->ctx->dc->debug.psr_power_use_phy_fsm;
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copy_settings_data->psr_level = psr_context->psr_level.u32all;
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copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations;
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copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations;
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copy_settings_data->frame_delay = psr_context->frame_delay;
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copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq;
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copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline;
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copy_settings_data->debug.u32All = 0;
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copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
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copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1;
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copy_settings_data->debug.bitfields.force_full_frame_update = 0;
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if (psr_context->su_granularity_required == 0)
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copy_settings_data->su_y_granularity = 0;
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else
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copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
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copy_settings_data->line_capture_indication = 0;
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copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
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copy_settings_data->rate_control_caps = psr_context->rate_control_caps;
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copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
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copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
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copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
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copy_settings_data->panel_inst = panel_inst;
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copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
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/**
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* WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update)
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* Note that PSRSU+DSC is still under development.
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*/
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if (copy_settings_data->dsc_enable_status &&
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link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &&
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!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
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sizeof(DP_SINK_DEVICE_STR_ID_1)))
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link->psr_settings.force_ffu_mode = 1;
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else
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link->psr_settings.force_ffu_mode = 0;
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copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode;
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if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
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!link->dc->debug.disable_fec) &&
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(link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
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!link->panel_config.dsc.disable_dsc_edp &&
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link->dc->caps.edp_dsc_support)) &&
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link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &&
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(!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
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sizeof(DP_SINK_DEVICE_STR_ID_1)) ||
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!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_2,
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sizeof(DP_SINK_DEVICE_STR_ID_2))))
|
|
copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1;
|
|
else
|
|
copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0;
|
|
|
|
//WA for PSR1 on specific TCON, require frame delay for frame re-lock
|
|
copy_settings_data->relock_delay_frame_cnt = 0;
|
|
if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
|
|
copy_settings_data->relock_delay_frame_cnt = 2;
|
|
copy_settings_data->dsc_slice_height = psr_context->dsc_slice_height;
|
|
|
|
dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
|
|
dc_dmub_srv_cmd_execute(dc->dmub_srv);
|
|
dc_dmub_srv_wait_idle(dc->dmub_srv);
|
|
|
|
return true;
|
|
}
|
|
|
|
/*
|
|
* Send command to PSR to force static ENTER and ignore all state changes until exit
|
|
*/
|
|
static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst)
|
|
{
|
|
union dmub_rb_cmd cmd;
|
|
struct dc_context *dc = dmub->ctx;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
|
|
cmd.psr_force_static.psr_force_static_data.panel_inst = panel_inst;
|
|
cmd.psr_force_static.psr_force_static_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
|
|
cmd.psr_force_static.header.type = DMUB_CMD__PSR;
|
|
cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC;
|
|
cmd.psr_enable.header.payload_bytes = 0;
|
|
|
|
dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
|
|
dc_dmub_srv_cmd_execute(dc->dmub_srv);
|
|
dc_dmub_srv_wait_idle(dc->dmub_srv);
|
|
}
|
|
|
|
/*
|
|
* Get PSR residency from firmware.
|
|
*/
|
|
static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst)
|
|
{
|
|
struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
|
|
uint16_t param = (uint16_t)(panel_inst << 8);
|
|
|
|
/* Send gpint command and wait for ack */
|
|
dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30);
|
|
|
|
dmub_srv_get_gpint_response(srv, residency);
|
|
}
|
|
|
|
static const struct dmub_psr_funcs psr_funcs = {
|
|
.psr_copy_settings = dmub_psr_copy_settings,
|
|
.psr_enable = dmub_psr_enable,
|
|
.psr_get_state = dmub_psr_get_state,
|
|
.psr_set_level = dmub_psr_set_level,
|
|
.psr_force_static = dmub_psr_force_static,
|
|
.psr_get_residency = dmub_psr_get_residency,
|
|
.psr_set_sink_vtotal_in_psr_active = dmub_psr_set_sink_vtotal_in_psr_active,
|
|
.psr_set_power_opt = dmub_psr_set_power_opt,
|
|
};
|
|
|
|
/*
|
|
* Construct PSR object.
|
|
*/
|
|
static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
|
|
{
|
|
psr->ctx = ctx;
|
|
psr->funcs = &psr_funcs;
|
|
}
|
|
|
|
/*
|
|
* Allocate and initialize PSR object.
|
|
*/
|
|
struct dmub_psr *dmub_psr_create(struct dc_context *ctx)
|
|
{
|
|
struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL);
|
|
|
|
if (psr == NULL) {
|
|
BREAK_TO_DEBUGGER();
|
|
return NULL;
|
|
}
|
|
|
|
dmub_psr_construct(psr, ctx);
|
|
|
|
return psr;
|
|
}
|
|
|
|
/*
|
|
* Deallocate PSR object.
|
|
*/
|
|
void dmub_psr_destroy(struct dmub_psr **dmub)
|
|
{
|
|
kfree(*dmub);
|
|
*dmub = NULL;
|
|
}
|