433 lines
13 KiB
C
433 lines
13 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "core_types.h"
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#include "reg_helper.h"
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#include "dcn20_dpp.h"
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#include "basics/conversion.h"
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#define NUM_PHASES 64
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#define HORZ_MAX_TAPS 8
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#define VERT_MAX_TAPS 8
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#define BLACK_OFFSET_RGB_Y 0x0
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#define BLACK_OFFSET_CBCR 0x8000
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#define REG(reg)\
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dpp->tf_regs->reg
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#define CTX \
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dpp->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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dpp->tf_shift->field_name, dpp->tf_mask->field_name
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void dpp20_read_state(struct dpp *dpp_base,
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struct dcn_dpp_state *s)
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{
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struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
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REG_GET(DPP_CONTROL,
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DPP_CLOCK_ENABLE, &s->is_enabled);
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REG_GET(CM_DGAM_CONTROL,
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CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
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// BGAM has no ROM, and definition is different, can't reuse same dump
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//REG_GET(CM_BLNDGAM_CONTROL,
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// CM_BLNDGAM_LUT_MODE, &s->rgam_lut_mode);
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REG_GET(CM_GAMUT_REMAP_CONTROL,
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CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
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if (s->gamut_remap_mode) {
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s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
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s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
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s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
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s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
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s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
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s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
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}
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}
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void dpp2_power_on_obuf(
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struct dpp *dpp_base,
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bool power_on)
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{
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struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
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REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);
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REG_UPDATE(OBUF_MEM_PWR_CTRL,
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OBUF_MEM_PWR_FORCE, power_on == true ? 0:1);
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REG_UPDATE(DSCL_MEM_PWR_CTRL,
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LUT_MEM_PWR_FORCE, power_on == true ? 0:1);
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}
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void dpp2_dummy_program_input_lut(
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struct dpp *dpp_base,
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const struct dc_gamma *gamma)
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{}
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static void dpp2_cnv_setup (
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struct dpp *dpp_base,
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enum surface_pixel_format format,
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enum expansion_mode mode,
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struct dc_csc_transform input_csc_color_matrix,
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enum dc_color_space input_color_space,
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struct cnv_alpha_2bit_lut *alpha_2bit_lut)
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{
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struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
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uint32_t pixel_format = 0;
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uint32_t alpha_en = 1;
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enum dc_color_space color_space = COLOR_SPACE_SRGB;
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enum dcn20_input_csc_select select = DCN2_ICSC_SELECT_BYPASS;
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bool force_disable_cursor = false;
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struct out_csc_color_matrix tbl_entry;
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uint32_t is_2bit = 0;
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int i = 0;
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REG_SET_2(FORMAT_CONTROL, 0,
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CNVC_BYPASS, 0,
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FORMAT_EXPANSION_MODE, mode);
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//hardcode default
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//FORMAT_CONTROL. FORMAT_CNV16 default 0: U0.16/S.1.15; 1: U1.15/ S.1.14
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//FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN default 0: disabled 1: enabled
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//FORMAT_CONTROL. CLAMP_POSITIVE default 0: disabled 1: enabled
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//FORMAT_CONTROL. CLAMP_POSITIVE_C default 0: disabled 1: enabled
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REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
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REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
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REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
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REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
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switch (format) {
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
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pixel_format = 1;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
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pixel_format = 3;
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alpha_en = 0;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
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pixel_format = 8;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
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pixel_format = 10;
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is_2bit = 1;
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
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force_disable_cursor = false;
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pixel_format = 65;
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color_space = COLOR_SPACE_YCBCR709;
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select = DCN2_ICSC_SELECT_ICSC_A;
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
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force_disable_cursor = true;
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pixel_format = 64;
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color_space = COLOR_SPACE_YCBCR709;
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select = DCN2_ICSC_SELECT_ICSC_A;
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
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force_disable_cursor = true;
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pixel_format = 67;
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color_space = COLOR_SPACE_YCBCR709;
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select = DCN2_ICSC_SELECT_ICSC_A;
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
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force_disable_cursor = true;
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pixel_format = 66;
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color_space = COLOR_SPACE_YCBCR709;
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select = DCN2_ICSC_SELECT_ICSC_A;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
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pixel_format = 26; /* ARGB16161616_UNORM */
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
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pixel_format = 24;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
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pixel_format = 25;
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
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pixel_format = 12;
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color_space = COLOR_SPACE_YCBCR709;
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select = DCN2_ICSC_SELECT_ICSC_A;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
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pixel_format = 112;
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alpha_en = 0;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
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pixel_format = 113;
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alpha_en = 0;
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
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pixel_format = 114;
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color_space = COLOR_SPACE_YCBCR709;
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select = DCN2_ICSC_SELECT_ICSC_A;
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is_2bit = 1;
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
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pixel_format = 115;
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color_space = COLOR_SPACE_YCBCR709;
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select = DCN2_ICSC_SELECT_ICSC_A;
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is_2bit = 1;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
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pixel_format = 118;
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alpha_en = 0;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
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pixel_format = 119;
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alpha_en = 0;
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break;
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default:
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break;
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}
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/* Set default color space based on format if none is given. */
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color_space = input_color_space ? input_color_space : color_space;
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if (is_2bit == 1 && alpha_2bit_lut != NULL) {
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REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
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REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
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REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
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REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
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}
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REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
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CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
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REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
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// if input adjustments exist, program icsc with those values
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if (input_csc_color_matrix.enable_adjustment
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== true) {
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for (i = 0; i < 12; i++)
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tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
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tbl_entry.color_space = input_color_space;
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if (color_space >= COLOR_SPACE_YCBCR601)
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select = DCN2_ICSC_SELECT_ICSC_A;
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else
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select = DCN2_ICSC_SELECT_BYPASS;
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dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry);
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} else
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dpp2_program_input_csc(dpp_base, color_space, select, NULL);
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if (force_disable_cursor) {
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REG_UPDATE(CURSOR_CONTROL,
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CURSOR_ENABLE, 0);
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REG_UPDATE(CURSOR0_CONTROL,
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CUR0_ENABLE, 0);
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}
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dpp2_power_on_obuf(dpp_base, true);
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}
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/*compute the maximum number of lines that we can fit in the line buffer*/
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void dscl2_calc_lb_num_partitions(
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const struct scaler_data *scl_data,
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enum lb_memory_config lb_config,
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int *num_part_y,
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int *num_part_c)
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{
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int memory_line_size_y, memory_line_size_c, memory_line_size_a,
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lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
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int line_size = scl_data->viewport.width < scl_data->recout.width ?
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scl_data->viewport.width : scl_data->recout.width;
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int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
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scl_data->viewport_c.width : scl_data->recout.width;
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if (line_size == 0)
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line_size = 1;
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if (line_size_c == 0)
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line_size_c = 1;
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memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */
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memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */
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memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
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if (lb_config == LB_MEMORY_CONFIG_1) {
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lb_memory_size = 970;
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lb_memory_size_c = 970;
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lb_memory_size_a = 970;
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} else if (lb_config == LB_MEMORY_CONFIG_2) {
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lb_memory_size = 1290;
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lb_memory_size_c = 1290;
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lb_memory_size_a = 1290;
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} else if (lb_config == LB_MEMORY_CONFIG_3) {
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/* 420 mode: using 3rd mem from Y, Cr and Cb */
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lb_memory_size = 970 + 1290 + 484 + 484 + 484;
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lb_memory_size_c = 970 + 1290;
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lb_memory_size_a = 970 + 1290 + 484;
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} else {
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lb_memory_size = 970 + 1290 + 484;
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lb_memory_size_c = 970 + 1290 + 484;
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lb_memory_size_a = 970 + 1290 + 484;
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}
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*num_part_y = lb_memory_size / memory_line_size_y;
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*num_part_c = lb_memory_size_c / memory_line_size_c;
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num_partitions_a = lb_memory_size_a / memory_line_size_a;
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if (scl_data->lb_params.alpha_en
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&& (num_partitions_a < *num_part_y))
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*num_part_y = num_partitions_a;
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if (*num_part_y > 64)
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*num_part_y = 64;
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if (*num_part_c > 64)
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*num_part_c = 64;
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}
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void dpp2_cnv_set_alpha_keyer(
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struct dpp *dpp_base,
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struct cnv_color_keyer_params *color_keyer)
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{
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struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
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REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_EN, color_keyer->color_keyer_en);
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REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, color_keyer->color_keyer_mode);
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REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, color_keyer->color_keyer_alpha_low);
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REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, color_keyer->color_keyer_alpha_high);
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REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, color_keyer->color_keyer_red_low);
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REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, color_keyer->color_keyer_red_high);
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REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, color_keyer->color_keyer_green_low);
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REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, color_keyer->color_keyer_green_high);
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REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, color_keyer->color_keyer_blue_low);
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REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, color_keyer->color_keyer_blue_high);
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}
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void dpp2_set_cursor_attributes(
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struct dpp *dpp_base,
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struct dc_cursor_attributes *cursor_attributes)
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{
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enum dc_cursor_color_format color_format = cursor_attributes->color_format;
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struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
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int cur_rom_en = 0;
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if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
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color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
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if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
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cur_rom_en = 1;
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}
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}
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REG_UPDATE_3(CURSOR0_CONTROL,
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CUR0_MODE, color_format,
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CUR0_EXPANSION_MODE, 0,
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CUR0_ROM_EN, cur_rom_en);
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if (color_format == CURSOR_MODE_MONO) {
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/* todo: clarify what to program these to */
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REG_UPDATE(CURSOR0_COLOR0,
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CUR0_COLOR0, 0x00000000);
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REG_UPDATE(CURSOR0_COLOR1,
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CUR0_COLOR1, 0xFFFFFFFF);
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}
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}
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void oppn20_dummy_program_regamma_pwl(
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struct dpp *dpp,
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const struct pwl_params *params,
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enum opp_regamma mode)
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{}
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static struct dpp_funcs dcn20_dpp_funcs = {
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.dpp_read_state = dpp20_read_state,
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.dpp_reset = dpp_reset,
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.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
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.dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps,
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.dpp_set_gamut_remap = dpp2_cm_set_gamut_remap,
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.dpp_set_csc_adjustment = NULL,
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.dpp_set_csc_default = NULL,
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.dpp_program_regamma_pwl = oppn20_dummy_program_regamma_pwl,
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.dpp_set_degamma = dpp2_set_degamma,
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.dpp_program_input_lut = dpp2_dummy_program_input_lut,
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.dpp_full_bypass = dpp1_full_bypass,
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.dpp_setup = dpp2_cnv_setup,
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.dpp_program_degamma_pwl = dpp2_set_degamma_pwl,
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.dpp_program_blnd_lut = dpp20_program_blnd_lut,
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.dpp_program_shaper_lut = dpp20_program_shaper,
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.dpp_program_3dlut = dpp20_program_3dlut,
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.dpp_program_bias_and_scale = NULL,
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.dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
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.set_cursor_attributes = dpp2_set_cursor_attributes,
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.set_cursor_position = dpp1_set_cursor_position,
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.set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
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.dpp_dppclk_control = dpp1_dppclk_control,
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.dpp_set_hdr_multiplier = dpp2_set_hdr_multiplier,
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};
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static struct dpp_caps dcn20_dpp_cap = {
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.dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
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.dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
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};
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bool dpp2_construct(
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struct dcn20_dpp *dpp,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn2_dpp_registers *tf_regs,
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const struct dcn2_dpp_shift *tf_shift,
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const struct dcn2_dpp_mask *tf_mask)
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{
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dpp->base.ctx = ctx;
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dpp->base.inst = inst;
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dpp->base.funcs = &dcn20_dpp_funcs;
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dpp->base.caps = &dcn20_dpp_cap;
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dpp->tf_regs = tf_regs;
|
|
dpp->tf_shift = tf_shift;
|
|
dpp->tf_mask = tf_mask;
|
|
|
|
dpp->lb_pixel_depth_supported =
|
|
LB_PIXEL_DEPTH_18BPP |
|
|
LB_PIXEL_DEPTH_24BPP |
|
|
LB_PIXEL_DEPTH_30BPP |
|
|
LB_PIXEL_DEPTH_36BPP;
|
|
|
|
dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
|
|
dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
|
|
|
|
return true;
|
|
}
|
|
|