531 lines
17 KiB
C
531 lines
17 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dcn30_hubp.h"
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#include "dm_services.h"
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#include "dce_calcs.h"
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#include "reg_helper.h"
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#include "basics/conversion.h"
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#include "dcn20/dcn20_hubp.h"
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#include "dcn21/dcn21_hubp.h"
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#define REG(reg)\
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hubp2->hubp_regs->reg
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#define CTX \
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hubp2->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
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void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
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struct vm_system_aperture_param *apt)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
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PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
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PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
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// The format of default addr is 48:12 of the 48 bit addr
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mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
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// The format of high/low are 48:18 of the 48 bit addr
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mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
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mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
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REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
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MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
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REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
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MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
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REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
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ENABLE_L1_TLB, 1,
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SYSTEM_ACCESS_MODE, 0x3);
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}
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bool hubp3_program_surface_flip_and_addr(
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struct hubp *hubp,
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const struct dc_plane_address *address,
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bool flip_immediate)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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//program flip type
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REG_UPDATE(DCSURF_FLIP_CONTROL,
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SURFACE_FLIP_TYPE, flip_immediate);
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// Program VMID reg
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if (flip_immediate == 0)
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REG_UPDATE(VMID_SETTINGS_0,
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VMID, address->vmid);
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if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
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REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0);
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REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
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} else {
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// turn off stereo if not in stereo
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REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
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REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
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}
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/* HW automatically latch rest of address register on write to
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* DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
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*
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* program high first and then the low addr, order matters!
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*/
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switch (address->type) {
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case PLN_ADDR_TYPE_GRAPHICS:
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/* DCN1.0 does not support const color
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* TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
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* base on address->grph.dcc_const_color
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* x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
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* x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
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*/
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if (address->grph.addr.quad_part == 0)
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break;
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REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
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PRIMARY_SURFACE_TMZ, address->tmz_surface,
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PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
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if (address->grph.meta_addr.quad_part != 0) {
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
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PRIMARY_META_SURFACE_ADDRESS_HIGH,
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address->grph.meta_addr.high_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
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PRIMARY_META_SURFACE_ADDRESS,
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address->grph.meta_addr.low_part);
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}
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
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PRIMARY_SURFACE_ADDRESS_HIGH,
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address->grph.addr.high_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
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PRIMARY_SURFACE_ADDRESS,
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address->grph.addr.low_part);
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break;
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case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
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if (address->video_progressive.luma_addr.quad_part == 0
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|| address->video_progressive.chroma_addr.quad_part == 0)
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break;
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REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
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PRIMARY_SURFACE_TMZ, address->tmz_surface,
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PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
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PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
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PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
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if (address->video_progressive.luma_meta_addr.quad_part != 0) {
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
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PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
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address->video_progressive.chroma_meta_addr.high_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
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PRIMARY_META_SURFACE_ADDRESS_C,
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address->video_progressive.chroma_meta_addr.low_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
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PRIMARY_META_SURFACE_ADDRESS_HIGH,
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address->video_progressive.luma_meta_addr.high_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
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PRIMARY_META_SURFACE_ADDRESS,
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address->video_progressive.luma_meta_addr.low_part);
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}
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
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PRIMARY_SURFACE_ADDRESS_HIGH_C,
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address->video_progressive.chroma_addr.high_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
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PRIMARY_SURFACE_ADDRESS_C,
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address->video_progressive.chroma_addr.low_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
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PRIMARY_SURFACE_ADDRESS_HIGH,
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address->video_progressive.luma_addr.high_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
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PRIMARY_SURFACE_ADDRESS,
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address->video_progressive.luma_addr.low_part);
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break;
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case PLN_ADDR_TYPE_GRPH_STEREO:
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if (address->grph_stereo.left_addr.quad_part == 0)
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break;
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if (address->grph_stereo.right_addr.quad_part == 0)
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break;
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REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
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PRIMARY_SURFACE_TMZ, address->tmz_surface,
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PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
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PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
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PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
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SECONDARY_SURFACE_TMZ, address->tmz_surface,
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SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
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SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
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SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
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if (address->grph_stereo.right_meta_addr.quad_part != 0) {
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REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, 0,
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SECONDARY_META_SURFACE_ADDRESS_HIGH_C,
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address->grph_stereo.right_alpha_meta_addr.high_part);
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REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, 0,
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SECONDARY_META_SURFACE_ADDRESS_C,
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address->grph_stereo.right_alpha_meta_addr.low_part);
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REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
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SECONDARY_META_SURFACE_ADDRESS_HIGH,
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address->grph_stereo.right_meta_addr.high_part);
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REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
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SECONDARY_META_SURFACE_ADDRESS,
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address->grph_stereo.right_meta_addr.low_part);
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}
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if (address->grph_stereo.left_meta_addr.quad_part != 0) {
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
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PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
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address->grph_stereo.left_alpha_meta_addr.high_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
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PRIMARY_META_SURFACE_ADDRESS_C,
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address->grph_stereo.left_alpha_meta_addr.low_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
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PRIMARY_META_SURFACE_ADDRESS_HIGH,
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address->grph_stereo.left_meta_addr.high_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
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PRIMARY_META_SURFACE_ADDRESS,
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address->grph_stereo.left_meta_addr.low_part);
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}
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REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0,
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SECONDARY_SURFACE_ADDRESS_HIGH_C,
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address->grph_stereo.right_alpha_addr.high_part);
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REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0,
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SECONDARY_SURFACE_ADDRESS_C,
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address->grph_stereo.right_alpha_addr.low_part);
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REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
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SECONDARY_SURFACE_ADDRESS_HIGH,
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address->grph_stereo.right_addr.high_part);
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REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
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SECONDARY_SURFACE_ADDRESS,
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address->grph_stereo.right_addr.low_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
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PRIMARY_SURFACE_ADDRESS_HIGH_C,
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address->grph_stereo.left_alpha_addr.high_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
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PRIMARY_SURFACE_ADDRESS_C,
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address->grph_stereo.left_alpha_addr.low_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
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PRIMARY_SURFACE_ADDRESS_HIGH,
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address->grph_stereo.left_addr.high_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
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PRIMARY_SURFACE_ADDRESS,
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address->grph_stereo.left_addr.low_part);
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break;
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case PLN_ADDR_TYPE_RGBEA:
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if (address->rgbea.addr.quad_part == 0
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|| address->rgbea.alpha_addr.quad_part == 0)
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break;
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REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
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PRIMARY_SURFACE_TMZ, address->tmz_surface,
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PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
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PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
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PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
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if (address->rgbea.meta_addr.quad_part != 0) {
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
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PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
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address->rgbea.alpha_meta_addr.high_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
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PRIMARY_META_SURFACE_ADDRESS_C,
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address->rgbea.alpha_meta_addr.low_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
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PRIMARY_META_SURFACE_ADDRESS_HIGH,
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address->rgbea.meta_addr.high_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
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PRIMARY_META_SURFACE_ADDRESS,
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address->rgbea.meta_addr.low_part);
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}
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
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PRIMARY_SURFACE_ADDRESS_HIGH_C,
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address->rgbea.alpha_addr.high_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
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PRIMARY_SURFACE_ADDRESS_C,
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address->rgbea.alpha_addr.low_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
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PRIMARY_SURFACE_ADDRESS_HIGH,
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address->rgbea.addr.high_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
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PRIMARY_SURFACE_ADDRESS,
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address->rgbea.addr.low_part);
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break;
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default:
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BREAK_TO_DEBUGGER();
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break;
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}
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hubp->request_address = *address;
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return true;
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}
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static void hubp3_program_tiling(
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struct dcn20_hubp *hubp2,
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const union dc_tiling_info *info,
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const enum surface_pixel_format pixel_format)
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{
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REG_UPDATE_4(DCSURF_ADDR_CONFIG,
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NUM_PIPES, log_2(info->gfx9.num_pipes),
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PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
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MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),
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NUM_PKRS, log_2(info->gfx9.num_pkrs));
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REG_UPDATE_3(DCSURF_TILING_CONFIG,
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SW_MODE, info->gfx9.swizzle,
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META_LINEAR, info->gfx9.meta_linear,
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PIPE_ALIGNED, info->gfx9.pipe_aligned);
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}
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void hubp3_dcc_control(struct hubp *hubp, bool enable,
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enum hubp_ind_block_size blk_size)
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{
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uint32_t dcc_en = enable ? 1 : 0;
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
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PRIMARY_SURFACE_DCC_EN, dcc_en,
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PRIMARY_SURFACE_DCC_IND_BLK, blk_size,
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SECONDARY_SURFACE_DCC_EN, dcc_en,
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SECONDARY_SURFACE_DCC_IND_BLK, blk_size);
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}
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void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,
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struct dc_plane_dcc_param *dcc)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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REG_UPDATE_6(DCSURF_SURFACE_CONTROL,
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PRIMARY_SURFACE_DCC_EN, dcc->enable,
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PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,
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PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c,
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SECONDARY_SURFACE_DCC_EN, dcc->enable,
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SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,
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SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c);
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}
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void hubp3_dmdata_set_attributes(
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struct hubp *hubp,
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const struct dc_dmdata_attributes *attr)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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/*always HW mode */
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REG_UPDATE(DMDATA_CNTL,
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DMDATA_MODE, 1);
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/* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */
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REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);
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/* toggle DMDATA_UPDATED and set repeat and size */
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REG_UPDATE(DMDATA_CNTL,
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DMDATA_UPDATED, 0);
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REG_UPDATE_3(DMDATA_CNTL,
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DMDATA_UPDATED, 1,
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DMDATA_REPEAT, attr->dmdata_repeat,
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DMDATA_SIZE, attr->dmdata_size);
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/* set DMDATA address */
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REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
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REG_UPDATE(DMDATA_ADDRESS_HIGH,
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DMDATA_ADDRESS_HIGH, attr->address.high_part);
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REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);
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}
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void hubp3_program_surface_config(
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struct hubp *hubp,
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enum surface_pixel_format format,
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union dc_tiling_info *tiling_info,
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struct plane_size *plane_size,
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enum dc_rotation_angle rotation,
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struct dc_plane_dcc_param *dcc,
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bool horizontal_mirror,
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unsigned int compat_level)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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hubp3_dcc_control_sienna_cichlid(hubp, dcc);
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hubp3_program_tiling(hubp2, tiling_info, format);
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hubp2_program_size(hubp, format, plane_size, dcc);
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hubp2_program_rotation(hubp, rotation, horizontal_mirror);
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hubp2_program_pixel_format(hubp, format);
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}
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|
|
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static void hubp3_program_deadline(
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struct hubp *hubp,
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struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
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struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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|
|
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hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
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REG_UPDATE(DCN_DMDATA_VM_CNTL,
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REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata);
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}
|
|
|
|
void hubp3_read_state(struct hubp *hubp)
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|
{
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|
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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|
struct dcn_hubp_state *s = &hubp2->state;
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struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
|
|
|
|
hubp2_read_state_common(hubp);
|
|
|
|
REG_GET_7(DCHUBP_REQ_SIZE_CONFIG,
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|
CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
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|
MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
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META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
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|
MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
|
|
DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
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|
SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
|
|
PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
|
|
|
|
REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C,
|
|
CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
|
|
MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
|
|
META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
|
|
MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
|
|
DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
|
|
SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
|
|
PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
|
|
|
|
}
|
|
|
|
void hubp3_setup(
|
|
struct hubp *hubp,
|
|
struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
|
|
struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
|
|
struct _vcs_dpi_display_rq_regs_st *rq_regs,
|
|
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
|
|
{
|
|
/* otg is locked when this func is called. Register are double buffered.
|
|
* disable the requestors is not needed
|
|
*/
|
|
hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
|
|
hubp21_program_requestor(hubp, rq_regs);
|
|
hubp3_program_deadline(hubp, dlg_attr, ttu_attr);
|
|
}
|
|
|
|
void hubp3_init(struct hubp *hubp)
|
|
{
|
|
// DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
|
|
// This is a chicken bit to enable the ECO fix.
|
|
|
|
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
|
|
//hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
|
|
REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
|
|
}
|
|
|
|
static struct hubp_funcs dcn30_hubp_funcs = {
|
|
.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
|
|
.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
|
|
.hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
|
|
.hubp_program_surface_config = hubp3_program_surface_config,
|
|
.hubp_is_flip_pending = hubp2_is_flip_pending,
|
|
.hubp_setup = hubp3_setup,
|
|
.hubp_setup_interdependent = hubp2_setup_interdependent,
|
|
.hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
|
|
.set_blank = hubp2_set_blank,
|
|
.set_blank_regs = hubp2_set_blank_regs,
|
|
.dcc_control = hubp3_dcc_control,
|
|
.mem_program_viewport = min_set_viewport,
|
|
.set_cursor_attributes = hubp2_cursor_set_attributes,
|
|
.set_cursor_position = hubp2_cursor_set_position,
|
|
.hubp_clk_cntl = hubp2_clk_cntl,
|
|
.hubp_vtg_sel = hubp2_vtg_sel,
|
|
.dmdata_set_attributes = hubp3_dmdata_set_attributes,
|
|
.dmdata_load = hubp2_dmdata_load,
|
|
.dmdata_status_done = hubp2_dmdata_status_done,
|
|
.hubp_read_state = hubp3_read_state,
|
|
.hubp_clear_underflow = hubp2_clear_underflow,
|
|
.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
|
|
.hubp_init = hubp3_init,
|
|
.hubp_in_blank = hubp1_in_blank,
|
|
.hubp_soft_reset = hubp1_soft_reset,
|
|
.hubp_set_flip_int = hubp1_set_flip_int,
|
|
};
|
|
|
|
bool hubp3_construct(
|
|
struct dcn20_hubp *hubp2,
|
|
struct dc_context *ctx,
|
|
uint32_t inst,
|
|
const struct dcn_hubp2_registers *hubp_regs,
|
|
const struct dcn_hubp2_shift *hubp_shift,
|
|
const struct dcn_hubp2_mask *hubp_mask)
|
|
{
|
|
hubp2->base.funcs = &dcn30_hubp_funcs;
|
|
hubp2->base.ctx = ctx;
|
|
hubp2->hubp_regs = hubp_regs;
|
|
hubp2->hubp_shift = hubp_shift;
|
|
hubp2->hubp_mask = hubp_mask;
|
|
hubp2->base.inst = inst;
|
|
hubp2->base.opp_id = OPP_ID_INVALID;
|
|
hubp2->base.mpcc_id = 0xf;
|
|
|
|
return true;
|
|
}
|