178 lines
5.8 KiB
C
178 lines
5.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_DISPLAY_POWER_WELL_H__
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#define __INTEL_DISPLAY_POWER_WELL_H__
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#include <linux/types.h>
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#include "intel_display_power.h"
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#include "intel_dpio_phy.h"
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struct drm_i915_private;
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struct i915_power_well;
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#define for_each_power_well(__dev_priv, __power_well) \
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for ((__power_well) = (__dev_priv)->display.power.domains.power_wells; \
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(__power_well) - (__dev_priv)->display.power.domains.power_wells < \
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(__dev_priv)->display.power.domains.power_well_count; \
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(__power_well)++)
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#define for_each_power_well_reverse(__dev_priv, __power_well) \
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for ((__power_well) = (__dev_priv)->display.power.domains.power_wells + \
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(__dev_priv)->display.power.domains.power_well_count - 1; \
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(__power_well) - (__dev_priv)->display.power.domains.power_wells >= 0; \
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(__power_well)--)
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/*
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* i915_power_well_id:
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*
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* IDs used to look up power wells. Power wells accessed directly bypassing
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* the power domains framework must be assigned a unique ID. The rest of power
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* wells must be assigned DISP_PW_ID_NONE.
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*/
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enum i915_power_well_id {
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DISP_PW_ID_NONE = 0, /* must be kept zero */
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VLV_DISP_PW_DISP2D,
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BXT_DISP_PW_DPIO_CMN_A,
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VLV_DISP_PW_DPIO_CMN_BC,
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GLK_DISP_PW_DPIO_CMN_C,
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CHV_DISP_PW_DPIO_CMN_D,
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HSW_DISP_PW_GLOBAL,
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SKL_DISP_PW_MISC_IO,
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SKL_DISP_PW_1,
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SKL_DISP_PW_2,
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ICL_DISP_PW_3,
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SKL_DISP_DC_OFF,
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TGL_DISP_PW_TC_COLD_OFF,
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};
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struct i915_power_well_instance {
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const char *name;
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const struct i915_power_domain_list {
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const enum intel_display_power_domain *list;
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u8 count;
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} *domain_list;
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/* unique identifier for this power well */
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enum i915_power_well_id id;
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/*
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* Arbitraty data associated with this power well. Platform and power
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* well specific.
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*/
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union {
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struct {
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/*
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* request/status flag index in the PUNIT power well
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* control/status registers.
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*/
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u8 idx;
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} vlv;
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struct {
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enum dpio_phy phy;
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} bxt;
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struct {
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/*
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* request/status flag index in the power well
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* constrol/status registers.
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*/
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u8 idx;
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} hsw;
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struct {
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u8 aux_ch;
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} xelpdp;
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};
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};
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struct i915_power_well_desc {
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const struct i915_power_well_ops *ops;
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const struct i915_power_well_instance_list {
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const struct i915_power_well_instance *list;
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u8 count;
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} *instances;
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/* Mask of pipes whose IRQ logic is backed by the pw */
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u16 irq_pipe_mask:4;
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u16 always_on:1;
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/*
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* Instead of waiting for the status bit to ack enables,
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* just wait a specific amount of time and then consider
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* the well enabled.
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*/
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u16 fixed_enable_delay:1;
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/* The pw is backing the VGA functionality */
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u16 has_vga:1;
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u16 has_fuses:1;
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/*
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* The pw is for an ICL+ TypeC PHY port in
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* Thunderbolt mode.
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*/
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u16 is_tc_tbt:1;
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};
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struct i915_power_well {
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const struct i915_power_well_desc *desc;
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struct intel_power_domain_mask domains;
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/* power well enable/disable usage count */
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int count;
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/* cached hw enabled state */
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bool hw_enabled;
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/* index into desc->instances->list */
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u8 instance_idx;
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};
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struct i915_power_well *lookup_power_well(struct drm_i915_private *i915,
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enum i915_power_well_id id);
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void intel_power_well_enable(struct drm_i915_private *i915,
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struct i915_power_well *power_well);
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void intel_power_well_disable(struct drm_i915_private *i915,
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struct i915_power_well *power_well);
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void intel_power_well_sync_hw(struct drm_i915_private *i915,
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struct i915_power_well *power_well);
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void intel_power_well_get(struct drm_i915_private *i915,
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struct i915_power_well *power_well);
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void intel_power_well_put(struct drm_i915_private *i915,
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struct i915_power_well *power_well);
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bool intel_power_well_is_enabled(struct drm_i915_private *i915,
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struct i915_power_well *power_well);
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bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well);
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bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
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enum i915_power_well_id power_well_id);
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bool intel_power_well_is_always_on(struct i915_power_well *power_well);
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const char *intel_power_well_name(struct i915_power_well *power_well);
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struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well);
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int intel_power_well_refcount(struct i915_power_well *power_well);
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void chv_phy_powergate_lanes(struct intel_encoder *encoder,
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bool override, unsigned int mask);
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bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
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enum dpio_channel ch, bool override);
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void gen9_enable_dc5(struct drm_i915_private *dev_priv);
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void skl_enable_dc6(struct drm_i915_private *dev_priv);
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void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
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void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state);
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void gen9_disable_dc_states(struct drm_i915_private *dev_priv);
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void bxt_enable_dc9(struct drm_i915_private *dev_priv);
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void bxt_disable_dc9(struct drm_i915_private *dev_priv);
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extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
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extern const struct i915_power_well_ops chv_pipe_power_well_ops;
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extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops;
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extern const struct i915_power_well_ops i830_pipes_power_well_ops;
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extern const struct i915_power_well_ops hsw_power_well_ops;
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extern const struct i915_power_well_ops gen9_dc_off_power_well_ops;
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extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops;
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extern const struct i915_power_well_ops vlv_display_power_well_ops;
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extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops;
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extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
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extern const struct i915_power_well_ops icl_aux_power_well_ops;
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extern const struct i915_power_well_ops icl_ddi_power_well_ops;
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extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
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extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
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#endif
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