454 lines
10 KiB
C
454 lines
10 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include "gen7_renderclear.h"
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#include "i915_drv.h"
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#include "intel_gpu_commands.h"
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#include "intel_gt_regs.h"
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#define GT3_INLINE_DATA_DELAYS 0x1E00
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#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
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struct cb_kernel {
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const void *data;
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u32 size;
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};
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#define CB_KERNEL(name) { .data = (name), .size = sizeof(name) }
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#include "ivb_clear_kernel.c"
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static const struct cb_kernel cb_kernel_ivb = CB_KERNEL(ivb_clear_kernel);
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#include "hsw_clear_kernel.c"
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static const struct cb_kernel cb_kernel_hsw = CB_KERNEL(hsw_clear_kernel);
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struct batch_chunk {
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struct i915_vma *vma;
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u32 offset;
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u32 *start;
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u32 *end;
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u32 max_items;
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};
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struct batch_vals {
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u32 max_threads;
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u32 state_start;
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u32 surface_start;
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u32 surface_height;
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u32 surface_width;
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u32 size;
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};
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static int num_primitives(const struct batch_vals *bv)
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{
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/*
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* We need to saturate the GPU with work in order to dispatch
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* a shader on every HW thread, and clear the thread-local registers.
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* In short, we have to dispatch work faster than the shaders can
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* run in order to fill the EU and occupy each HW thread.
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*/
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return bv->max_threads;
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}
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static void
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batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
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{
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if (IS_HASWELL(i915)) {
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switch (INTEL_INFO(i915)->gt) {
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default:
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case 1:
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bv->max_threads = 70;
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break;
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case 2:
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bv->max_threads = 140;
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break;
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case 3:
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bv->max_threads = 280;
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break;
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}
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bv->surface_height = 16 * 16;
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bv->surface_width = 32 * 2 * 16;
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} else {
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switch (INTEL_INFO(i915)->gt) {
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default:
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case 1: /* including vlv */
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bv->max_threads = 36;
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break;
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case 2:
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bv->max_threads = 128;
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break;
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}
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bv->surface_height = 16 * 8;
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bv->surface_width = 32 * 16;
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}
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bv->state_start = round_up(SZ_1K + num_primitives(bv) * 64, SZ_4K);
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bv->surface_start = bv->state_start + SZ_4K;
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bv->size = bv->surface_start + bv->surface_height * bv->surface_width;
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}
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static void batch_init(struct batch_chunk *bc,
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struct i915_vma *vma,
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u32 *start, u32 offset, u32 max_bytes)
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{
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bc->vma = vma;
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bc->offset = offset;
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bc->start = start + bc->offset / sizeof(*bc->start);
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bc->end = bc->start;
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bc->max_items = max_bytes / sizeof(*bc->start);
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}
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static u32 batch_offset(const struct batch_chunk *bc, u32 *cs)
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{
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return (cs - bc->start) * sizeof(*bc->start) + bc->offset;
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}
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static u32 batch_addr(const struct batch_chunk *bc)
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{
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return i915_vma_offset(bc->vma);
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}
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static void batch_add(struct batch_chunk *bc, const u32 d)
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{
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GEM_BUG_ON((bc->end - bc->start) >= bc->max_items);
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*bc->end++ = d;
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}
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static u32 *batch_alloc_items(struct batch_chunk *bc, u32 align, u32 items)
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{
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u32 *map;
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if (align) {
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u32 *end = PTR_ALIGN(bc->end, align);
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memset32(bc->end, 0, end - bc->end);
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bc->end = end;
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}
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map = bc->end;
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bc->end += items;
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return map;
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}
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static u32 *batch_alloc_bytes(struct batch_chunk *bc, u32 align, u32 bytes)
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{
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GEM_BUG_ON(!IS_ALIGNED(bytes, sizeof(*bc->start)));
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return batch_alloc_items(bc, align, bytes / sizeof(*bc->start));
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}
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static u32
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gen7_fill_surface_state(struct batch_chunk *state,
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const u32 dst_offset,
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const struct batch_vals *bv)
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{
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u32 surface_h = bv->surface_height;
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u32 surface_w = bv->surface_width;
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u32 *cs = batch_alloc_items(state, 32, 8);
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u32 offset = batch_offset(state, cs);
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#define SURFACE_2D 1
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#define SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0
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#define RENDER_CACHE_READ_WRITE 1
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*cs++ = SURFACE_2D << 29 |
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(SURFACEFORMAT_B8G8R8A8_UNORM << 18) |
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(RENDER_CACHE_READ_WRITE << 8);
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*cs++ = batch_addr(state) + dst_offset;
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*cs++ = ((surface_h / 4 - 1) << 16) | (surface_w / 4 - 1);
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*cs++ = surface_w;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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#define SHADER_CHANNELS(r, g, b, a) \
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(((r) << 25) | ((g) << 22) | ((b) << 19) | ((a) << 16))
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*cs++ = SHADER_CHANNELS(4, 5, 6, 7);
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batch_advance(state, cs);
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return offset;
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}
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static u32
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gen7_fill_binding_table(struct batch_chunk *state,
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const struct batch_vals *bv)
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{
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u32 surface_start =
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gen7_fill_surface_state(state, bv->surface_start, bv);
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u32 *cs = batch_alloc_items(state, 32, 8);
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u32 offset = batch_offset(state, cs);
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*cs++ = surface_start - state->offset;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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batch_advance(state, cs);
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return offset;
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}
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static u32
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gen7_fill_kernel_data(struct batch_chunk *state,
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const u32 *data,
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const u32 size)
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{
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return batch_offset(state,
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memcpy(batch_alloc_bytes(state, 64, size),
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data, size));
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}
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static u32
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gen7_fill_interface_descriptor(struct batch_chunk *state,
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const struct batch_vals *bv,
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const struct cb_kernel *kernel,
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unsigned int count)
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{
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u32 kernel_offset =
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gen7_fill_kernel_data(state, kernel->data, kernel->size);
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u32 binding_table = gen7_fill_binding_table(state, bv);
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u32 *cs = batch_alloc_items(state, 32, 8 * count);
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u32 offset = batch_offset(state, cs);
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*cs++ = kernel_offset;
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*cs++ = (1 << 7) | (1 << 13);
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*cs++ = 0;
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*cs++ = (binding_table - state->offset) | 1;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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/* 1 - 63dummy idds */
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memset32(cs, 0x00, (count - 1) * 8);
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batch_advance(state, cs + (count - 1) * 8);
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return offset;
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}
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static void
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gen7_emit_state_base_address(struct batch_chunk *batch,
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u32 surface_state_base)
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{
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u32 *cs = batch_alloc_items(batch, 0, 10);
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*cs++ = STATE_BASE_ADDRESS | (10 - 2);
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/* general */
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*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;
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/* surface */
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*cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY;
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/* dynamic */
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*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;
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/* indirect */
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*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;
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/* instruction */
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*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;
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/* general/dynamic/indirect/instruction access Bound */
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*cs++ = 0;
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*cs++ = BASE_ADDRESS_MODIFY;
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*cs++ = 0;
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*cs++ = BASE_ADDRESS_MODIFY;
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batch_advance(batch, cs);
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}
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static void
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gen7_emit_vfe_state(struct batch_chunk *batch,
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const struct batch_vals *bv,
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u32 urb_size, u32 curbe_size,
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u32 mode)
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{
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u32 threads = bv->max_threads - 1;
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u32 *cs = batch_alloc_items(batch, 32, 8);
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*cs++ = MEDIA_VFE_STATE | (8 - 2);
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/* scratch buffer */
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*cs++ = 0;
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/* number of threads & urb entries for GPGPU vs Media Mode */
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*cs++ = threads << 16 | 1 << 8 | mode << 2;
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*cs++ = 0;
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/* urb entry size & curbe size in 256 bits unit */
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*cs++ = urb_size << 16 | curbe_size;
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/* scoreboard */
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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batch_advance(batch, cs);
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}
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static void
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gen7_emit_interface_descriptor_load(struct batch_chunk *batch,
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const u32 interface_descriptor,
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unsigned int count)
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{
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u32 *cs = batch_alloc_items(batch, 8, 4);
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*cs++ = MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2);
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*cs++ = 0;
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*cs++ = count * 8 * sizeof(*cs);
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/*
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* interface descriptor address - it is relative to the dynamics base
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* address
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*/
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*cs++ = interface_descriptor;
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batch_advance(batch, cs);
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}
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static void
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gen7_emit_media_object(struct batch_chunk *batch,
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unsigned int media_object_index)
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{
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unsigned int x_offset = (media_object_index % 16) * 64;
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unsigned int y_offset = (media_object_index / 16) * 16;
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unsigned int pkt = 6 + 3;
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u32 *cs;
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cs = batch_alloc_items(batch, 8, pkt);
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*cs++ = MEDIA_OBJECT | (pkt - 2);
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/* interface descriptor offset */
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*cs++ = 0;
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/* without indirect data */
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*cs++ = 0;
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*cs++ = 0;
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/* scoreboard */
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*cs++ = 0;
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*cs++ = 0;
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/* inline */
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*cs++ = y_offset << 16 | x_offset;
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*cs++ = 0;
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*cs++ = GT3_INLINE_DATA_DELAYS;
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batch_advance(batch, cs);
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}
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static void gen7_emit_pipeline_flush(struct batch_chunk *batch)
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{
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u32 *cs = batch_alloc_items(batch, 0, 4);
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*cs++ = GFX_OP_PIPE_CONTROL(4);
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*cs++ = PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
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PIPE_CONTROL_DEPTH_CACHE_FLUSH |
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PIPE_CONTROL_DC_FLUSH_ENABLE |
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PIPE_CONTROL_CS_STALL;
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*cs++ = 0;
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*cs++ = 0;
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batch_advance(batch, cs);
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}
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static void gen7_emit_pipeline_invalidate(struct batch_chunk *batch)
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{
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u32 *cs = batch_alloc_items(batch, 0, 10);
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/* ivb: Stall before STATE_CACHE_INVALIDATE */
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*cs++ = GFX_OP_PIPE_CONTROL(5);
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*cs++ = PIPE_CONTROL_STALL_AT_SCOREBOARD |
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PIPE_CONTROL_CS_STALL;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = GFX_OP_PIPE_CONTROL(5);
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*cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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batch_advance(batch, cs);
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}
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static void emit_batch(struct i915_vma * const vma,
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u32 *start,
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const struct batch_vals *bv)
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{
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struct drm_i915_private *i915 = vma->vm->i915;
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const unsigned int desc_count = 1;
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const unsigned int urb_size = 1;
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struct batch_chunk cmds, state;
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u32 descriptors;
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unsigned int i;
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batch_init(&cmds, vma, start, 0, bv->state_start);
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batch_init(&state, vma, start, bv->state_start, SZ_4K);
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descriptors = gen7_fill_interface_descriptor(&state, bv,
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IS_HASWELL(i915) ?
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&cb_kernel_hsw :
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&cb_kernel_ivb,
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desc_count);
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/* Reset inherited context registers */
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gen7_emit_pipeline_flush(&cmds);
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gen7_emit_pipeline_invalidate(&cmds);
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batch_add(&cmds, MI_LOAD_REGISTER_IMM(2));
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batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));
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batch_add(&cmds, 0xffff0000 |
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((IS_IVB_GT1(i915) || IS_VALLEYVIEW(i915)) ?
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HIZ_RAW_STALL_OPT_DISABLE :
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0));
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batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
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batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
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gen7_emit_pipeline_invalidate(&cmds);
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gen7_emit_pipeline_flush(&cmds);
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/* Switch to the media pipeline and our base address */
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gen7_emit_pipeline_invalidate(&cmds);
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batch_add(&cmds, PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
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batch_add(&cmds, MI_NOOP);
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gen7_emit_pipeline_invalidate(&cmds);
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gen7_emit_pipeline_flush(&cmds);
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gen7_emit_state_base_address(&cmds, descriptors);
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gen7_emit_pipeline_invalidate(&cmds);
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/* Set the clear-residual kernel state */
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gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0);
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gen7_emit_interface_descriptor_load(&cmds, descriptors, desc_count);
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/* Execute the kernel on all HW threads */
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for (i = 0; i < num_primitives(bv); i++)
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gen7_emit_media_object(&cmds, i);
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batch_add(&cmds, MI_BATCH_BUFFER_END);
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}
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int gen7_setup_clear_gpr_bb(struct intel_engine_cs * const engine,
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struct i915_vma * const vma)
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{
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struct batch_vals bv;
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u32 *batch;
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batch_get_defaults(engine->i915, &bv);
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if (!vma)
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return bv.size;
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GEM_BUG_ON(vma->obj->base.size < bv.size);
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batch = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
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if (IS_ERR(batch))
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return PTR_ERR(batch);
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emit_batch(vma, memset(batch, 0, bv.size), &bv);
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i915_gem_object_flush_map(vma->obj);
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__i915_gem_object_release_map(vma->obj);
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return 0;
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}
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