219 lines
6.8 KiB
C
219 lines
6.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2021-2022 Intel Corporation
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*/
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#ifndef _INTEL_GUC_CAPTURE_FWIF_H
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#define _INTEL_GUC_CAPTURE_FWIF_H
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#include <linux/types.h>
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#include "intel_guc_fwif.h"
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struct intel_guc;
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struct file;
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/**
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* struct __guc_capture_bufstate
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*
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* Book-keeping structure used to track read and write pointers
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* as we extract error capture data from the GuC-log-buffer's
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* error-capture region as a stream of dwords.
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*/
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struct __guc_capture_bufstate {
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u32 size;
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void *data;
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u32 rd;
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u32 wr;
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};
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/**
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* struct __guc_capture_parsed_output - extracted error capture node
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*
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* A single unit of extracted error-capture output data grouped together
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* at an engine-instance level. We keep these nodes in a linked list.
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* See cachelist and outlist below.
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*/
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struct __guc_capture_parsed_output {
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/*
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* A single set of 3 capture lists: a global-list
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* an engine-class-list and an engine-instance list.
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* outlist in __guc_capture_parsed_output will keep
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* a linked list of these nodes that will eventually
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* be detached from outlist and attached into to
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* i915_gpu_codedump in response to a context reset
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*/
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struct list_head link;
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bool is_partial;
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u32 eng_class;
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u32 eng_inst;
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u32 guc_id;
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u32 lrca;
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struct gcap_reg_list_info {
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u32 vfid;
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u32 num_regs;
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struct guc_mmio_reg *regs;
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} reginfo[GUC_CAPTURE_LIST_TYPE_MAX];
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#define GCAP_PARSED_REGLIST_INDEX_GLOBAL BIT(GUC_CAPTURE_LIST_TYPE_GLOBAL)
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#define GCAP_PARSED_REGLIST_INDEX_ENGCLASS BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS)
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#define GCAP_PARSED_REGLIST_INDEX_ENGINST BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE)
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};
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/**
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* struct guc_debug_capture_list_header / struct guc_debug_capture_list
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*
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* As part of ADS registration, these header structures (followed by
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* an array of 'struct guc_mmio_reg' entries) are used to register with
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* GuC microkernel the list of registers we want it to dump out prior
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* to a engine reset.
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*/
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struct guc_debug_capture_list_header {
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u32 info;
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#define GUC_CAPTURELISTHDR_NUMDESCR GENMASK(15, 0)
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} __packed;
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struct guc_debug_capture_list {
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struct guc_debug_capture_list_header header;
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struct guc_mmio_reg regs[];
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} __packed;
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/**
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* struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group
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*
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* intel_guc_capture module uses these structures to maintain static
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* tables (per unique platform) that consists of lists of registers
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* (offsets, names, flags,...) that are used at the ADS regisration
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* time as well as during runtime processing and reporting of error-
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* capture states generated by GuC just prior to engine reset events.
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*/
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struct __guc_mmio_reg_descr {
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i915_reg_t reg;
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u32 flags;
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u32 mask;
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const char *regname;
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};
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struct __guc_mmio_reg_descr_group {
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const struct __guc_mmio_reg_descr *list;
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u32 num_regs;
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u32 owner; /* see enum guc_capture_owner */
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u32 type; /* see enum guc_capture_type */
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u32 engine; /* as per MAX_ENGINE_CLASS */
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struct __guc_mmio_reg_descr *extlist; /* only used for steered registers */
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};
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/**
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* struct guc_state_capture_header_t / struct guc_state_capture_t /
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* guc_state_capture_group_header_t / guc_state_capture_group_t
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*
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* Prior to resetting engines that have hung or faulted, GuC microkernel
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* reports the engine error-state (register values that was read) by
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* logging them into the shared GuC log buffer using these hierarchy
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* of structures.
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*/
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struct guc_state_capture_header_t {
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u32 owner;
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#define CAP_HDR_CAPTURE_VFID GENMASK(7, 0)
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u32 info;
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#define CAP_HDR_CAPTURE_TYPE GENMASK(3, 0) /* see enum guc_capture_type */
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#define CAP_HDR_ENGINE_CLASS GENMASK(7, 4) /* see GUC_MAX_ENGINE_CLASSES */
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#define CAP_HDR_ENGINE_INSTANCE GENMASK(11, 8)
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u32 lrca; /* if type-instance, LRCA (address) that hung, else set to ~0 */
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u32 guc_id; /* if type-instance, context index of hung context, else set to ~0 */
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u32 num_mmios;
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#define CAP_HDR_NUM_MMIOS GENMASK(9, 0)
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} __packed;
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struct guc_state_capture_t {
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struct guc_state_capture_header_t header;
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struct guc_mmio_reg mmio_entries[];
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} __packed;
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enum guc_capture_group_types {
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GUC_STATE_CAPTURE_GROUP_TYPE_FULL,
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GUC_STATE_CAPTURE_GROUP_TYPE_PARTIAL,
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GUC_STATE_CAPTURE_GROUP_TYPE_MAX,
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};
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struct guc_state_capture_group_header_t {
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u32 owner;
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#define CAP_GRP_HDR_CAPTURE_VFID GENMASK(7, 0)
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u32 info;
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#define CAP_GRP_HDR_NUM_CAPTURES GENMASK(7, 0)
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#define CAP_GRP_HDR_CAPTURE_TYPE GENMASK(15, 8) /* guc_capture_group_types */
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} __packed;
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/* this is the top level structure where an error-capture dump starts */
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struct guc_state_capture_group_t {
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struct guc_state_capture_group_header_t grp_header;
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struct guc_state_capture_t capture_entries[];
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} __packed;
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/**
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* struct __guc_capture_ads_cache
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*
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* A structure to cache register lists that were populated and registered
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* with GuC at startup during ADS registration. This allows much quicker
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* GuC resets without re-parsing all the tables for the given gt.
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*/
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struct __guc_capture_ads_cache {
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bool is_valid;
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void *ptr;
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size_t size;
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int status;
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};
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/**
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* struct intel_guc_state_capture
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*
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* Internal context of the intel_guc_capture module.
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*/
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struct intel_guc_state_capture {
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/**
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* @reglists: static table of register lists used for error-capture state.
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*/
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const struct __guc_mmio_reg_descr_group *reglists;
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/**
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* @extlists: allocated table of steered register lists used for error-capture state.
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*
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* NOTE: steered registers have multiple instances depending on the HW configuration
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* (slices or dual-sub-slices) and thus depends on HW fuses discovered at startup
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*/
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struct __guc_mmio_reg_descr_group *extlists;
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/**
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* @ads_cache: cached register lists that is ADS format ready
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*/
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struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX]
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[GUC_CAPTURE_LIST_TYPE_MAX]
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[GUC_MAX_ENGINE_CLASSES];
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void *ads_null_cache;
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/**
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* @cachelist: Pool of pre-allocated nodes for error capture output
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*
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* We need this pool of pre-allocated nodes because we cannot
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* dynamically allocate new nodes when receiving the G2H notification
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* because the event handlers for all G2H event-processing is called
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* by the ct processing worker queue and when that queue is being
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* processed, there is no absoluate guarantee that we are not in the
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* midst of a GT reset operation (which doesn't allow allocations).
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*/
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struct list_head cachelist;
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#define PREALLOC_NODES_MAX_COUNT (3 * GUC_MAX_ENGINE_CLASSES * GUC_MAX_INSTANCES_PER_CLASS)
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#define PREALLOC_NODES_DEFAULT_NUMREGS 64
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int max_mmio_per_node;
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/**
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* @outlist: Pool of pre-allocated nodes for error capture output
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*
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* A linked list of parsed GuC error-capture output data before
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* reporting with formatting via i915_gpu_coredump. Each node in this linked list shall
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* contain a single engine-capture including global, engine-class and
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* engine-instance register dumps as per guc_capture_parsed_output_node
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*/
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struct list_head outlist;
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};
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#endif /* _INTEL_GUC_CAPTURE_FWIF_H */
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