180 lines
5.6 KiB
C
180 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2019 NXP.
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*/
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#ifndef __DCSS_PRV_H__
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#define __DCSS_PRV_H__
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#include <drm/drm_fourcc.h>
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#include <drm/drm_plane.h>
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#include <linux/io.h>
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#include <linux/pm.h>
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#include <video/videomode.h>
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#define SET 0x04
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#define CLR 0x08
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#define TGL 0x0C
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#define dcss_writel(v, c) writel((v), (c))
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#define dcss_readl(c) readl(c)
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#define dcss_set(v, c) writel((v), (c) + SET)
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#define dcss_clr(v, c) writel((v), (c) + CLR)
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#define dcss_toggle(v, c) writel((v), (c) + TGL)
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static inline void dcss_update(u32 v, u32 m, void __iomem *c)
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{
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writel((readl(c) & ~(m)) | (v), (c));
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}
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#define DCSS_DBG_REG(reg) {.name = #reg, .ofs = reg}
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enum {
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DCSS_IMX8MQ = 0,
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};
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struct dcss_type_data {
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const char *name;
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u32 blkctl_ofs;
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u32 ctxld_ofs;
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u32 rdsrc_ofs;
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u32 wrscl_ofs;
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u32 dtg_ofs;
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u32 scaler_ofs;
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u32 ss_ofs;
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u32 dpr_ofs;
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u32 dtrc_ofs;
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u32 dec400d_ofs;
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u32 hdr10_ofs;
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};
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struct dcss_debug_reg {
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char *name;
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u32 ofs;
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};
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enum dcss_ctxld_ctx_type {
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CTX_DB,
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CTX_SB_HP, /* high-priority */
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CTX_SB_LP, /* low-priority */
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};
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struct dcss_dev {
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struct device *dev;
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const struct dcss_type_data *devtype;
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struct device_node *of_port;
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u32 start_addr;
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struct dcss_blkctl *blkctl;
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struct dcss_ctxld *ctxld;
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struct dcss_dpr *dpr;
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struct dcss_dtg *dtg;
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struct dcss_ss *ss;
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struct dcss_hdr10 *hdr10;
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struct dcss_scaler *scaler;
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struct dcss_dtrc *dtrc;
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struct dcss_dec400d *dec400d;
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struct dcss_wrscl *wrscl;
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struct dcss_rdsrc *rdsrc;
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struct clk *apb_clk;
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struct clk *axi_clk;
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struct clk *pix_clk;
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struct clk *rtrm_clk;
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struct clk *dtrc_clk;
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struct clk *pll_src_clk;
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struct clk *pll_phy_ref_clk;
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bool hdmi_output;
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void (*disable_callback)(void *data);
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struct completion disable_completion;
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};
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struct dcss_dev *dcss_drv_dev_to_dcss(struct device *dev);
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struct drm_device *dcss_drv_dev_to_drm(struct device *dev);
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struct dcss_dev *dcss_dev_create(struct device *dev, bool hdmi_output);
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void dcss_dev_destroy(struct dcss_dev *dcss);
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void dcss_enable_dtg_and_ss(struct dcss_dev *dcss);
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void dcss_disable_dtg_and_ss(struct dcss_dev *dcss);
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extern const struct dev_pm_ops dcss_dev_pm_ops;
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/* BLKCTL */
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int dcss_blkctl_init(struct dcss_dev *dcss, unsigned long blkctl_base);
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void dcss_blkctl_cfg(struct dcss_blkctl *blkctl);
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void dcss_blkctl_exit(struct dcss_blkctl *blkctl);
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/* CTXLD */
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int dcss_ctxld_init(struct dcss_dev *dcss, unsigned long ctxld_base);
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void dcss_ctxld_exit(struct dcss_ctxld *ctxld);
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void dcss_ctxld_write(struct dcss_ctxld *ctxld, u32 ctx_id,
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u32 val, u32 reg_idx);
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int dcss_ctxld_resume(struct dcss_ctxld *dcss_ctxld);
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int dcss_ctxld_suspend(struct dcss_ctxld *dcss_ctxld);
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void dcss_ctxld_write_irqsafe(struct dcss_ctxld *ctlxd, u32 ctx_id, u32 val,
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u32 reg_ofs);
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void dcss_ctxld_kick(struct dcss_ctxld *ctxld);
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bool dcss_ctxld_is_flushed(struct dcss_ctxld *ctxld);
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int dcss_ctxld_enable(struct dcss_ctxld *ctxld);
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void dcss_ctxld_register_completion(struct dcss_ctxld *ctxld,
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struct completion *dis_completion);
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void dcss_ctxld_assert_locked(struct dcss_ctxld *ctxld);
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/* DPR */
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int dcss_dpr_init(struct dcss_dev *dcss, unsigned long dpr_base);
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void dcss_dpr_exit(struct dcss_dpr *dpr);
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void dcss_dpr_write_sysctrl(struct dcss_dpr *dpr);
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void dcss_dpr_set_res(struct dcss_dpr *dpr, int ch_num, u32 xres, u32 yres);
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void dcss_dpr_addr_set(struct dcss_dpr *dpr, int ch_num, u32 luma_base_addr,
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u32 chroma_base_addr, u16 pitch);
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void dcss_dpr_enable(struct dcss_dpr *dpr, int ch_num, bool en);
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void dcss_dpr_format_set(struct dcss_dpr *dpr, int ch_num,
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const struct drm_format_info *format, u64 modifier);
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void dcss_dpr_set_rotation(struct dcss_dpr *dpr, int ch_num, u32 rotation);
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/* DTG */
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int dcss_dtg_init(struct dcss_dev *dcss, unsigned long dtg_base);
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void dcss_dtg_exit(struct dcss_dtg *dtg);
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bool dcss_dtg_vblank_irq_valid(struct dcss_dtg *dtg);
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void dcss_dtg_vblank_irq_enable(struct dcss_dtg *dtg, bool en);
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void dcss_dtg_vblank_irq_clear(struct dcss_dtg *dtg);
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void dcss_dtg_sync_set(struct dcss_dtg *dtg, struct videomode *vm);
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void dcss_dtg_css_set(struct dcss_dtg *dtg);
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void dcss_dtg_enable(struct dcss_dtg *dtg);
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void dcss_dtg_shutoff(struct dcss_dtg *dtg);
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bool dcss_dtg_is_enabled(struct dcss_dtg *dtg);
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void dcss_dtg_ctxld_kick_irq_enable(struct dcss_dtg *dtg, bool en);
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bool dcss_dtg_global_alpha_changed(struct dcss_dtg *dtg, int ch_num, int alpha);
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void dcss_dtg_plane_alpha_set(struct dcss_dtg *dtg, int ch_num,
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const struct drm_format_info *format, int alpha);
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void dcss_dtg_plane_pos_set(struct dcss_dtg *dtg, int ch_num,
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int px, int py, int pw, int ph);
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void dcss_dtg_ch_enable(struct dcss_dtg *dtg, int ch_num, bool en);
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/* SUBSAM */
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int dcss_ss_init(struct dcss_dev *dcss, unsigned long subsam_base);
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void dcss_ss_exit(struct dcss_ss *ss);
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void dcss_ss_enable(struct dcss_ss *ss);
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void dcss_ss_shutoff(struct dcss_ss *ss);
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void dcss_ss_subsam_set(struct dcss_ss *ss);
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void dcss_ss_sync_set(struct dcss_ss *ss, struct videomode *vm,
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bool phsync, bool pvsync);
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/* SCALER */
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int dcss_scaler_init(struct dcss_dev *dcss, unsigned long scaler_base);
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void dcss_scaler_exit(struct dcss_scaler *scl);
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void dcss_scaler_set_filter(struct dcss_scaler *scl, int ch_num,
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enum drm_scaling_filter scaling_filter);
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void dcss_scaler_setup(struct dcss_scaler *scl, int ch_num,
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const struct drm_format_info *format,
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int src_xres, int src_yres, int dst_xres, int dst_yres,
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u32 vrefresh_hz);
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void dcss_scaler_ch_enable(struct dcss_scaler *scl, int ch_num, bool en);
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int dcss_scaler_get_min_max_ratios(struct dcss_scaler *scl, int ch_num,
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int *min, int *max);
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void dcss_scaler_write_sclctrl(struct dcss_scaler *scl);
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#endif /* __DCSS_PRV_H__ */
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