894 lines
25 KiB
C
894 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <drm/bridge/dw_hdmi.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_device.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_print.h>
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#include <linux/videodev2.h>
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#include "meson_drv.h"
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#include "meson_dw_hdmi.h"
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#include "meson_registers.h"
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#define DRIVER_NAME "meson-dw-hdmi"
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#define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
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/**
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* DOC: HDMI Output
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*
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* HDMI Output is composed of :
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*
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* - A Synopsys DesignWare HDMI Controller IP
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* - A TOP control block controlling the Clocks and PHY
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* - A custom HDMI PHY in order convert video to TMDS signal
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*
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* .. code::
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*
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* ___________________________________
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* | HDMI TOP |<= HPD
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* |___________________________________|
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* | | |
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* | Synopsys HDMI | HDMI PHY |=> TMDS
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* | Controller |________________|
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* |___________________________________|<=> DDC
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*
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*
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* The HDMI TOP block only supports HPD sensing.
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* The Synopsys HDMI Controller interrupt is routed
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* through the TOP Block interrupt.
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* Communication to the TOP Block and the Synopsys
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* HDMI Controller is done a pair of addr+read/write
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* registers.
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* The HDMI PHY is configured by registers in the
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* HHI register block.
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*
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* Pixel data arrives in 4:4:4 format from the VENC
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* block and the VPU HDMI mux selects either the ENCI
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* encoder for the 576i or 480i formats or the ENCP
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* encoder for all the other formats including
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* interlaced HD formats.
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* The VENC uses a DVI encoder on top of the ENCI
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* or ENCP encoders to generate DVI timings for the
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* HDMI controller.
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*
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* GXBB, GXL and GXM embeds the Synopsys DesignWare
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* HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
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* audio source interfaces.
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*
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* We handle the following features :
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*
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* - HPD Rise & Fall interrupt
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* - HDMI Controller Interrupt
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* - HDMI PHY Init for 480i to 1080p60
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* - VENC & HDMI Clock setup for 480i to 1080p60
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* - VENC Mode setup for 480i to 1080p60
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*
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* What is missing :
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*
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* - PHY, Clock and Mode setup for 2k && 4k modes
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* - SDDC Scrambling mode for HDMI 2.0a
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* - HDCP Setup
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* - CEC Management
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*/
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/* TOP Block Communication Channel */
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#define HDMITX_TOP_ADDR_REG 0x0
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#define HDMITX_TOP_DATA_REG 0x4
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#define HDMITX_TOP_CTRL_REG 0x8
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#define HDMITX_TOP_G12A_OFFSET 0x8000
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/* Controller Communication Channel */
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#define HDMITX_DWC_ADDR_REG 0x10
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#define HDMITX_DWC_DATA_REG 0x14
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#define HDMITX_DWC_CTRL_REG 0x18
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/* HHI Registers */
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#define HHI_MEM_PD_REG0 0x100 /* 0x40 */
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#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
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#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
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#define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
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#define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
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#define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
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#define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */
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#define HHI_HDMI_PHY_CNTL5 0x3b4 /* 0xed */
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static DEFINE_SPINLOCK(reg_lock);
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enum meson_venc_source {
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MESON_VENC_SOURCE_NONE = 0,
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MESON_VENC_SOURCE_ENCI = 1,
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MESON_VENC_SOURCE_ENCP = 2,
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};
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struct meson_dw_hdmi;
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struct meson_dw_hdmi_data {
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unsigned int (*top_read)(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr);
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void (*top_write)(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data);
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unsigned int (*dwc_read)(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr);
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void (*dwc_write)(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data);
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};
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struct meson_dw_hdmi {
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struct dw_hdmi_plat_data dw_plat_data;
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struct meson_drm *priv;
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struct device *dev;
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void __iomem *hdmitx;
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const struct meson_dw_hdmi_data *data;
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struct reset_control *hdmitx_apb;
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struct reset_control *hdmitx_ctrl;
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struct reset_control *hdmitx_phy;
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u32 irq_stat;
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struct dw_hdmi *hdmi;
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struct drm_bridge *bridge;
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};
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static inline int dw_hdmi_is_compatible(struct meson_dw_hdmi *dw_hdmi,
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const char *compat)
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{
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return of_device_is_compatible(dw_hdmi->dev->of_node, compat);
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}
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/* PHY (via TOP bridge) and Controller dedicated register interface */
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static unsigned int dw_hdmi_top_read(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr)
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{
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unsigned long flags;
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unsigned int data;
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spin_lock_irqsave(®_lock, flags);
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/* ADDR must be written twice */
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writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
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writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
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/* Read needs a second DATA read */
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data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
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data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
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spin_unlock_irqrestore(®_lock, flags);
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return data;
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}
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static unsigned int dw_hdmi_g12a_top_read(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr)
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{
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return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));
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}
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static inline void dw_hdmi_top_write(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data)
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{
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unsigned long flags;
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spin_lock_irqsave(®_lock, flags);
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/* ADDR must be written twice */
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writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
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writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
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/* Write needs single DATA write */
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writel(data, dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
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spin_unlock_irqrestore(®_lock, flags);
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}
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static inline void dw_hdmi_g12a_top_write(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data)
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{
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writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));
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}
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/* Helper to change specific bits in PHY registers */
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static inline void dw_hdmi_top_write_bits(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr,
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unsigned int mask,
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unsigned int val)
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{
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unsigned int data = dw_hdmi->data->top_read(dw_hdmi, addr);
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data &= ~mask;
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data |= val;
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dw_hdmi->data->top_write(dw_hdmi, addr, data);
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}
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static unsigned int dw_hdmi_dwc_read(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr)
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{
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unsigned long flags;
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unsigned int data;
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spin_lock_irqsave(®_lock, flags);
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/* ADDR must be written twice */
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writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
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writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
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/* Read needs a second DATA read */
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data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
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data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
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spin_unlock_irqrestore(®_lock, flags);
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return data;
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}
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static unsigned int dw_hdmi_g12a_dwc_read(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr)
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{
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return readb(dw_hdmi->hdmitx + addr);
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}
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static inline void dw_hdmi_dwc_write(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data)
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{
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unsigned long flags;
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spin_lock_irqsave(®_lock, flags);
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/* ADDR must be written twice */
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writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
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writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
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/* Write needs single DATA write */
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writel(data, dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
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spin_unlock_irqrestore(®_lock, flags);
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}
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static inline void dw_hdmi_g12a_dwc_write(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data)
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{
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writeb(data, dw_hdmi->hdmitx + addr);
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}
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/* Helper to change specific bits in controller registers */
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static inline void dw_hdmi_dwc_write_bits(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr,
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unsigned int mask,
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unsigned int val)
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{
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unsigned int data = dw_hdmi->data->dwc_read(dw_hdmi, addr);
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data &= ~mask;
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data |= val;
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dw_hdmi->data->dwc_write(dw_hdmi, addr, data);
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}
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/* Bridge */
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/* Setup PHY bandwidth modes */
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static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi,
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const struct drm_display_mode *mode,
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bool mode_is_420)
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{
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struct meson_drm *priv = dw_hdmi->priv;
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unsigned int pixel_clock = mode->clock;
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/* For 420, pixel clock is half unlike venc clock */
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if (mode_is_420) pixel_clock /= 2;
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if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
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dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) {
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if (pixel_clock >= 371250) {
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/* 5.94Gbps, 3.7125Gbps */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x333d3282);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2136315b);
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} else if (pixel_clock >= 297000) {
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/* 2.97Gbps */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303382);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2036315b);
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} else if (pixel_clock >= 148500) {
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/* 1.485Gbps */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303362);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2016315b);
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} else {
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/* 742.5Mbps, and below */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33604142);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x0016315b);
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}
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} else if (dw_hdmi_is_compatible(dw_hdmi,
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"amlogic,meson-gxbb-dw-hdmi")) {
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if (pixel_clock >= 371250) {
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/* 5.94Gbps, 3.7125Gbps */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33353245);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2100115b);
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} else if (pixel_clock >= 297000) {
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/* 2.97Gbps */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33634283);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0xb000115b);
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} else {
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/* 1.485Gbps, and below */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33632122);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2000115b);
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}
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} else if (dw_hdmi_is_compatible(dw_hdmi,
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"amlogic,meson-g12a-dw-hdmi")) {
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if (pixel_clock >= 371250) {
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/* 5.94Gbps, 3.7125Gbps */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x0000080b);
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} else if (pixel_clock >= 297000) {
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/* 2.97Gbps */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb6262);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003);
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} else {
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/* 1.485Gbps, and below */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb4242);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003);
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}
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}
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}
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static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *dw_hdmi)
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{
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struct meson_drm *priv = dw_hdmi->priv;
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/* Enable and software reset */
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regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf);
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mdelay(2);
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/* Enable and unreset */
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regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe);
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mdelay(2);
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}
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static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
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const struct drm_display_info *display,
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const struct drm_display_mode *mode)
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{
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struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
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bool is_hdmi2_sink = display->hdmi.scdc.supported;
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struct meson_drm *priv = dw_hdmi->priv;
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unsigned int wr_clk =
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readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING));
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bool mode_is_420 = false;
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DRM_DEBUG_DRIVER("\"%s\" div%d\n", mode->name,
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mode->clock > 340000 ? 40 : 10);
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if (drm_mode_is_420_only(display, mode) ||
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(!is_hdmi2_sink &&
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drm_mode_is_420_also(display, mode)))
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mode_is_420 = true;
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/* Enable clocks */
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regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
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/* Bring HDMITX MEM output of power down */
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regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);
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/* Bring out of reset */
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET, 0);
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/* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
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dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
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0x3, 0x3);
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/* Enable cec_clk and hdcp22_tmdsclk_en */
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dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
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0x3 << 4, 0x3 << 4);
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/* Enable normal output to PHY */
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
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/* TMDS pattern setup */
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if (mode->clock > 340000 && !mode_is_420) {
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
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0);
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
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0x03ff03ff);
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} else {
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
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0x001f001f);
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
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0x001f001f);
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}
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/* Load TMDS pattern */
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
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msleep(20);
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);
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/* Setup PHY parameters */
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meson_hdmi_phy_setup_mode(dw_hdmi, mode, mode_is_420);
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/* Setup PHY */
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regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
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0xffff << 16, 0x0390 << 16);
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/* BIT_INVERT */
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if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
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dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
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dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
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regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
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BIT(17), 0);
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else
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regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
|
|
BIT(17), BIT(17));
|
|
|
|
/* Disable clock, fifo, fifo_wr */
|
|
regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);
|
|
|
|
dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
|
|
|
|
msleep(100);
|
|
|
|
/* Reset PHY 3 times in a row */
|
|
meson_dw_hdmi_phy_reset(dw_hdmi);
|
|
meson_dw_hdmi_phy_reset(dw_hdmi);
|
|
meson_dw_hdmi_phy_reset(dw_hdmi);
|
|
|
|
/* Temporary Disable VENC video stream */
|
|
if (priv->venc.hdmi_use_enci)
|
|
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
|
|
else
|
|
writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
|
|
|
|
/* Temporary Disable HDMI video stream to HDMI-TX */
|
|
writel_bits_relaxed(0x3, 0,
|
|
priv->io_base + _REG(VPU_HDMI_SETTING));
|
|
writel_bits_relaxed(0xf << 8, 0,
|
|
priv->io_base + _REG(VPU_HDMI_SETTING));
|
|
|
|
/* Re-Enable VENC video stream */
|
|
if (priv->venc.hdmi_use_enci)
|
|
writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
|
|
else
|
|
writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
|
|
|
|
/* Push back HDMI clock settings */
|
|
writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8),
|
|
priv->io_base + _REG(VPU_HDMI_SETTING));
|
|
|
|
/* Enable and Select HDMI video source for HDMI-TX */
|
|
if (priv->venc.hdmi_use_enci)
|
|
writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI,
|
|
priv->io_base + _REG(VPU_HDMI_SETTING));
|
|
else
|
|
writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP,
|
|
priv->io_base + _REG(VPU_HDMI_SETTING));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi,
|
|
void *data)
|
|
{
|
|
struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
|
|
struct meson_drm *priv = dw_hdmi->priv;
|
|
|
|
DRM_DEBUG_DRIVER("\n");
|
|
|
|
regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
|
|
}
|
|
|
|
static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi,
|
|
void *data)
|
|
{
|
|
struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
|
|
|
|
return !!dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_STAT0) ?
|
|
connector_status_connected : connector_status_disconnected;
|
|
}
|
|
|
|
static void dw_hdmi_setup_hpd(struct dw_hdmi *hdmi,
|
|
void *data)
|
|
{
|
|
struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
|
|
|
|
/* Setup HPD Filter */
|
|
dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_HPD_FILTER,
|
|
(0xa << 12) | 0xa0);
|
|
|
|
/* Clear interrupts */
|
|
dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
|
|
HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL);
|
|
|
|
/* Unmask interrupts */
|
|
dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_INTR_MASKN,
|
|
HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL,
|
|
HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL);
|
|
}
|
|
|
|
static const struct dw_hdmi_phy_ops meson_dw_hdmi_phy_ops = {
|
|
.init = dw_hdmi_phy_init,
|
|
.disable = dw_hdmi_phy_disable,
|
|
.read_hpd = dw_hdmi_read_hpd,
|
|
.setup_hpd = dw_hdmi_setup_hpd,
|
|
};
|
|
|
|
static irqreturn_t dw_hdmi_top_irq(int irq, void *dev_id)
|
|
{
|
|
struct meson_dw_hdmi *dw_hdmi = dev_id;
|
|
u32 stat;
|
|
|
|
stat = dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_INTR_STAT);
|
|
dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, stat);
|
|
|
|
/* HPD Events, handle in the threaded interrupt handler */
|
|
if (stat & (HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL)) {
|
|
dw_hdmi->irq_stat = stat;
|
|
return IRQ_WAKE_THREAD;
|
|
}
|
|
|
|
/* HDMI Controller Interrupt */
|
|
if (stat & 1)
|
|
return IRQ_NONE;
|
|
|
|
/* TOFIX Handle HDCP Interrupts */
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/* Threaded interrupt handler to manage HPD events */
|
|
static irqreturn_t dw_hdmi_top_thread_irq(int irq, void *dev_id)
|
|
{
|
|
struct meson_dw_hdmi *dw_hdmi = dev_id;
|
|
u32 stat = dw_hdmi->irq_stat;
|
|
|
|
/* HPD Events */
|
|
if (stat & (HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL)) {
|
|
bool hpd_connected = false;
|
|
|
|
if (stat & HDMITX_TOP_INTR_HPD_RISE)
|
|
hpd_connected = true;
|
|
|
|
dw_hdmi_setup_rx_sense(dw_hdmi->hdmi, hpd_connected,
|
|
hpd_connected);
|
|
|
|
drm_helper_hpd_irq_event(dw_hdmi->bridge->dev);
|
|
drm_bridge_hpd_notify(dw_hdmi->bridge,
|
|
hpd_connected ? connector_status_connected
|
|
: connector_status_disconnected);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/* DW HDMI Regmap */
|
|
|
|
static int meson_dw_hdmi_reg_read(void *context, unsigned int reg,
|
|
unsigned int *result)
|
|
{
|
|
struct meson_dw_hdmi *dw_hdmi = context;
|
|
|
|
*result = dw_hdmi->data->dwc_read(dw_hdmi, reg);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static int meson_dw_hdmi_reg_write(void *context, unsigned int reg,
|
|
unsigned int val)
|
|
{
|
|
struct meson_dw_hdmi *dw_hdmi = context;
|
|
|
|
dw_hdmi->data->dwc_write(dw_hdmi, reg, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct regmap_config meson_dw_hdmi_regmap_config = {
|
|
.reg_bits = 32,
|
|
.val_bits = 8,
|
|
.reg_read = meson_dw_hdmi_reg_read,
|
|
.reg_write = meson_dw_hdmi_reg_write,
|
|
.max_register = 0x10000,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static const struct meson_dw_hdmi_data meson_dw_hdmi_gx_data = {
|
|
.top_read = dw_hdmi_top_read,
|
|
.top_write = dw_hdmi_top_write,
|
|
.dwc_read = dw_hdmi_dwc_read,
|
|
.dwc_write = dw_hdmi_dwc_write,
|
|
};
|
|
|
|
static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
|
|
.top_read = dw_hdmi_g12a_top_read,
|
|
.top_write = dw_hdmi_g12a_top_write,
|
|
.dwc_read = dw_hdmi_g12a_dwc_read,
|
|
.dwc_write = dw_hdmi_g12a_dwc_write,
|
|
};
|
|
|
|
static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)
|
|
{
|
|
struct meson_drm *priv = meson_dw_hdmi->priv;
|
|
|
|
/* Enable clocks */
|
|
regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
|
|
|
|
/* Bring HDMITX MEM output of power down */
|
|
regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);
|
|
|
|
/* Reset HDMITX APB & TX & PHY */
|
|
reset_control_reset(meson_dw_hdmi->hdmitx_apb);
|
|
reset_control_reset(meson_dw_hdmi->hdmitx_ctrl);
|
|
reset_control_reset(meson_dw_hdmi->hdmitx_phy);
|
|
|
|
/* Enable APB3 fail on error */
|
|
if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
|
|
writel_bits_relaxed(BIT(15), BIT(15),
|
|
meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG);
|
|
writel_bits_relaxed(BIT(15), BIT(15),
|
|
meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG);
|
|
}
|
|
|
|
/* Bring out of reset */
|
|
meson_dw_hdmi->data->top_write(meson_dw_hdmi,
|
|
HDMITX_TOP_SW_RESET, 0);
|
|
|
|
msleep(20);
|
|
|
|
meson_dw_hdmi->data->top_write(meson_dw_hdmi,
|
|
HDMITX_TOP_CLK_CNTL, 0xff);
|
|
|
|
/* Enable HDMI-TX Interrupt */
|
|
meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
|
|
HDMITX_TOP_INTR_CORE);
|
|
|
|
meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN,
|
|
HDMITX_TOP_INTR_CORE);
|
|
|
|
}
|
|
|
|
static void meson_disable_clk(void *data)
|
|
{
|
|
clk_disable_unprepare(data);
|
|
}
|
|
|
|
static int meson_enable_clk(struct device *dev, char *name)
|
|
{
|
|
struct clk *clk;
|
|
int ret;
|
|
|
|
clk = devm_clk_get(dev, name);
|
|
if (IS_ERR(clk)) {
|
|
dev_err(dev, "Unable to get %s pclk\n", name);
|
|
return PTR_ERR(clk);
|
|
}
|
|
|
|
ret = clk_prepare_enable(clk);
|
|
if (!ret)
|
|
ret = devm_add_action_or_reset(dev, meson_disable_clk, clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
const struct meson_dw_hdmi_data *match;
|
|
struct meson_dw_hdmi *meson_dw_hdmi;
|
|
struct drm_device *drm = data;
|
|
struct meson_drm *priv = drm->dev_private;
|
|
struct dw_hdmi_plat_data *dw_plat_data;
|
|
int irq;
|
|
int ret;
|
|
|
|
DRM_DEBUG_DRIVER("\n");
|
|
|
|
match = of_device_get_match_data(&pdev->dev);
|
|
if (!match) {
|
|
dev_err(&pdev->dev, "failed to get match data\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
meson_dw_hdmi = devm_kzalloc(dev, sizeof(*meson_dw_hdmi),
|
|
GFP_KERNEL);
|
|
if (!meson_dw_hdmi)
|
|
return -ENOMEM;
|
|
|
|
meson_dw_hdmi->priv = priv;
|
|
meson_dw_hdmi->dev = dev;
|
|
meson_dw_hdmi->data = match;
|
|
dw_plat_data = &meson_dw_hdmi->dw_plat_data;
|
|
|
|
ret = devm_regulator_get_enable_optional(dev, "hdmi");
|
|
if (ret < 0 && ret != -ENODEV)
|
|
return ret;
|
|
|
|
meson_dw_hdmi->hdmitx_apb = devm_reset_control_get_exclusive(dev,
|
|
"hdmitx_apb");
|
|
if (IS_ERR(meson_dw_hdmi->hdmitx_apb)) {
|
|
dev_err(dev, "Failed to get hdmitx_apb reset\n");
|
|
return PTR_ERR(meson_dw_hdmi->hdmitx_apb);
|
|
}
|
|
|
|
meson_dw_hdmi->hdmitx_ctrl = devm_reset_control_get_exclusive(dev,
|
|
"hdmitx");
|
|
if (IS_ERR(meson_dw_hdmi->hdmitx_ctrl)) {
|
|
dev_err(dev, "Failed to get hdmitx reset\n");
|
|
return PTR_ERR(meson_dw_hdmi->hdmitx_ctrl);
|
|
}
|
|
|
|
meson_dw_hdmi->hdmitx_phy = devm_reset_control_get_exclusive(dev,
|
|
"hdmitx_phy");
|
|
if (IS_ERR(meson_dw_hdmi->hdmitx_phy)) {
|
|
dev_err(dev, "Failed to get hdmitx_phy reset\n");
|
|
return PTR_ERR(meson_dw_hdmi->hdmitx_phy);
|
|
}
|
|
|
|
meson_dw_hdmi->hdmitx = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(meson_dw_hdmi->hdmitx))
|
|
return PTR_ERR(meson_dw_hdmi->hdmitx);
|
|
|
|
ret = meson_enable_clk(dev, "isfr");
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = meson_enable_clk(dev, "iahb");
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = meson_enable_clk(dev, "venci");
|
|
if (ret)
|
|
return ret;
|
|
|
|
dw_plat_data->regm = devm_regmap_init(dev, NULL, meson_dw_hdmi,
|
|
&meson_dw_hdmi_regmap_config);
|
|
if (IS_ERR(dw_plat_data->regm))
|
|
return PTR_ERR(dw_plat_data->regm);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
ret = devm_request_threaded_irq(dev, irq, dw_hdmi_top_irq,
|
|
dw_hdmi_top_thread_irq, IRQF_SHARED,
|
|
"dw_hdmi_top_irq", meson_dw_hdmi);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to request hdmi top irq\n");
|
|
return ret;
|
|
}
|
|
|
|
meson_dw_hdmi_init(meson_dw_hdmi);
|
|
|
|
/* Bridge / Connector */
|
|
|
|
dw_plat_data->priv_data = meson_dw_hdmi;
|
|
dw_plat_data->phy_ops = &meson_dw_hdmi_phy_ops;
|
|
dw_plat_data->phy_name = "meson_dw_hdmi_phy";
|
|
dw_plat_data->phy_data = meson_dw_hdmi;
|
|
dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709;
|
|
dw_plat_data->ycbcr_420_allowed = true;
|
|
dw_plat_data->disable_cec = true;
|
|
dw_plat_data->output_port = 1;
|
|
|
|
if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
|
|
dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
|
|
dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
|
|
dw_plat_data->use_drm_infoframe = true;
|
|
|
|
platform_set_drvdata(pdev, meson_dw_hdmi);
|
|
|
|
meson_dw_hdmi->hdmi = dw_hdmi_probe(pdev, &meson_dw_hdmi->dw_plat_data);
|
|
if (IS_ERR(meson_dw_hdmi->hdmi))
|
|
return PTR_ERR(meson_dw_hdmi->hdmi);
|
|
|
|
meson_dw_hdmi->bridge = of_drm_find_bridge(pdev->dev.of_node);
|
|
|
|
DRM_DEBUG_DRIVER("HDMI controller initialized\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void meson_dw_hdmi_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct meson_dw_hdmi *meson_dw_hdmi = dev_get_drvdata(dev);
|
|
|
|
dw_hdmi_unbind(meson_dw_hdmi->hdmi);
|
|
}
|
|
|
|
static const struct component_ops meson_dw_hdmi_ops = {
|
|
.bind = meson_dw_hdmi_bind,
|
|
.unbind = meson_dw_hdmi_unbind,
|
|
};
|
|
|
|
static int __maybe_unused meson_dw_hdmi_pm_suspend(struct device *dev)
|
|
{
|
|
struct meson_dw_hdmi *meson_dw_hdmi = dev_get_drvdata(dev);
|
|
|
|
if (!meson_dw_hdmi)
|
|
return 0;
|
|
|
|
/* Reset TOP */
|
|
meson_dw_hdmi->data->top_write(meson_dw_hdmi,
|
|
HDMITX_TOP_SW_RESET, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused meson_dw_hdmi_pm_resume(struct device *dev)
|
|
{
|
|
struct meson_dw_hdmi *meson_dw_hdmi = dev_get_drvdata(dev);
|
|
|
|
if (!meson_dw_hdmi)
|
|
return 0;
|
|
|
|
meson_dw_hdmi_init(meson_dw_hdmi);
|
|
|
|
dw_hdmi_resume(meson_dw_hdmi->hdmi);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int meson_dw_hdmi_probe(struct platform_device *pdev)
|
|
{
|
|
return component_add(&pdev->dev, &meson_dw_hdmi_ops);
|
|
}
|
|
|
|
static int meson_dw_hdmi_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &meson_dw_hdmi_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops meson_dw_hdmi_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(meson_dw_hdmi_pm_suspend,
|
|
meson_dw_hdmi_pm_resume)
|
|
};
|
|
|
|
static const struct of_device_id meson_dw_hdmi_of_table[] = {
|
|
{ .compatible = "amlogic,meson-gxbb-dw-hdmi",
|
|
.data = &meson_dw_hdmi_gx_data },
|
|
{ .compatible = "amlogic,meson-gxl-dw-hdmi",
|
|
.data = &meson_dw_hdmi_gx_data },
|
|
{ .compatible = "amlogic,meson-gxm-dw-hdmi",
|
|
.data = &meson_dw_hdmi_gx_data },
|
|
{ .compatible = "amlogic,meson-g12a-dw-hdmi",
|
|
.data = &meson_dw_hdmi_g12a_data },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, meson_dw_hdmi_of_table);
|
|
|
|
static struct platform_driver meson_dw_hdmi_platform_driver = {
|
|
.probe = meson_dw_hdmi_probe,
|
|
.remove = meson_dw_hdmi_remove,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.of_match_table = meson_dw_hdmi_of_table,
|
|
.pm = &meson_dw_hdmi_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(meson_dw_hdmi_platform_driver);
|
|
|
|
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_LICENSE("GPL");
|