136 lines
3.4 KiB
C
136 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/dma-mapping.h>
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#include "meson_drv.h"
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#include "meson_registers.h"
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#include "meson_rdma.h"
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/*
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* The VPU embeds a "Register DMA" that can write a sequence of registers
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* on the VPU AHB bus, either manually or triggered by an internal IRQ
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* event like VSYNC or a line input counter.
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* The initial implementation handles a single channel (over 8), triggered
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* by the VSYNC irq and does not handle the RDMA irq.
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*/
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#define RDMA_DESC_SIZE (sizeof(uint32_t) * 2)
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int meson_rdma_init(struct meson_drm *priv)
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{
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if (!priv->rdma.addr) {
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/* Allocate a PAGE buffer */
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priv->rdma.addr =
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dma_alloc_coherent(priv->dev, SZ_4K,
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&priv->rdma.addr_dma,
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GFP_KERNEL);
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if (!priv->rdma.addr)
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return -ENOMEM;
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}
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priv->rdma.offset = 0;
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writel_relaxed(RDMA_CTRL_SW_RESET,
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priv->io_base + _REG(RDMA_CTRL));
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writel_relaxed(RDMA_DEFAULT_CONFIG |
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FIELD_PREP(RDMA_CTRL_AHB_WR_BURST, 3) |
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FIELD_PREP(RDMA_CTRL_AHB_RD_BURST, 0),
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priv->io_base + _REG(RDMA_CTRL));
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return 0;
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}
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void meson_rdma_free(struct meson_drm *priv)
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{
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if (!priv->rdma.addr && !priv->rdma.addr_dma)
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return;
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meson_rdma_stop(priv);
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dma_free_coherent(priv->dev, SZ_4K,
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priv->rdma.addr, priv->rdma.addr_dma);
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priv->rdma.addr = NULL;
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priv->rdma.addr_dma = (dma_addr_t)0;
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}
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void meson_rdma_setup(struct meson_drm *priv)
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{
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/* Channel 1: Write Flag, No Address Increment */
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writel_bits_relaxed(RDMA_ACCESS_RW_FLAG_CHAN1 |
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RDMA_ACCESS_ADDR_INC_CHAN1,
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RDMA_ACCESS_RW_FLAG_CHAN1,
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priv->io_base + _REG(RDMA_ACCESS_AUTO));
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}
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void meson_rdma_stop(struct meson_drm *priv)
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{
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writel_bits_relaxed(RDMA_IRQ_CLEAR_CHAN1,
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RDMA_IRQ_CLEAR_CHAN1,
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priv->io_base + _REG(RDMA_CTRL));
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/* Stop Channel 1 */
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writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1,
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FIELD_PREP(RDMA_ACCESS_ADDR_INC_CHAN1,
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RDMA_ACCESS_TRIGGER_STOP),
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priv->io_base + _REG(RDMA_ACCESS_AUTO));
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}
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void meson_rdma_reset(struct meson_drm *priv)
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{
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meson_rdma_stop(priv);
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priv->rdma.offset = 0;
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}
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static void meson_rdma_writel(struct meson_drm *priv, uint32_t val,
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uint32_t reg)
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{
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if (priv->rdma.offset >= (SZ_4K / RDMA_DESC_SIZE)) {
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dev_warn_once(priv->dev, "%s: overflow\n", __func__);
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return;
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}
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priv->rdma.addr[priv->rdma.offset++] = reg;
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priv->rdma.addr[priv->rdma.offset++] = val;
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}
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/*
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* This will add the register to the RDMA buffer and write it to the
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* hardware at the same time.
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* When meson_rdma_flush is called, the RDMA will replay the register
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* writes in order.
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*/
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void meson_rdma_writel_sync(struct meson_drm *priv, uint32_t val, uint32_t reg)
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{
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meson_rdma_writel(priv, val, reg);
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writel_relaxed(val, priv->io_base + _REG(reg));
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}
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void meson_rdma_flush(struct meson_drm *priv)
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{
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meson_rdma_stop(priv);
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/* Start of Channel 1 register writes buffer */
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writel(priv->rdma.addr_dma,
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priv->io_base + _REG(RDMA_AHB_START_ADDR_1));
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/* Last byte on Channel 1 register writes buffer */
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writel(priv->rdma.addr_dma + (priv->rdma.offset * RDMA_DESC_SIZE) - 1,
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priv->io_base + _REG(RDMA_AHB_END_ADDR_1));
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/* Trigger Channel 1 on VSYNC event */
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writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1,
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FIELD_PREP(RDMA_ACCESS_TRIGGER_CHAN1,
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RDMA_ACCESS_TRIGGER_VSYNC),
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priv->io_base + _REG(RDMA_ACCESS_AUTO));
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priv->rdma.offset = 0;
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}
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