605 lines
19 KiB
C
605 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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*/
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#include "a3xx_gpu.h"
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#define A3XX_INT0_MASK \
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(A3XX_INT0_RBBM_AHB_ERROR | \
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A3XX_INT0_RBBM_ATB_BUS_OVERFLOW | \
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A3XX_INT0_CP_T0_PACKET_IN_IB | \
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A3XX_INT0_CP_OPCODE_ERROR | \
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A3XX_INT0_CP_RESERVED_BIT_ERROR | \
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A3XX_INT0_CP_HW_FAULT | \
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A3XX_INT0_CP_IB1_INT | \
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A3XX_INT0_CP_IB2_INT | \
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A3XX_INT0_CP_RB_INT | \
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A3XX_INT0_CP_REG_PROTECT_FAULT | \
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A3XX_INT0_CP_AHB_ERROR_HALT | \
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A3XX_INT0_CACHE_FLUSH_TS | \
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A3XX_INT0_UCHE_OOB_ACCESS)
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extern bool hang_debug;
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static void a3xx_dump(struct msm_gpu *gpu);
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static bool a3xx_idle(struct msm_gpu *gpu);
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static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
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{
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struct msm_ringbuffer *ring = submit->ring;
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unsigned int i;
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for (i = 0; i < submit->nr_cmds; i++) {
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switch (submit->cmd[i].type) {
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case MSM_SUBMIT_CMD_IB_TARGET_BUF:
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/* ignore IB-targets */
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break;
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case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
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/* ignore if there has not been a ctx switch: */
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if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno)
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break;
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fallthrough;
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case MSM_SUBMIT_CMD_BUF:
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OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);
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OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
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OUT_RING(ring, submit->cmd[i].size);
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OUT_PKT2(ring);
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break;
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}
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}
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OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
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OUT_RING(ring, submit->seqno);
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/* Flush HLSQ lazy updates to make sure there is nothing
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* pending for indirect loads after the timestamp has
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* passed:
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*/
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OUT_PKT3(ring, CP_EVENT_WRITE, 1);
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OUT_RING(ring, HLSQ_FLUSH);
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/* wait for idle before cache flush/interrupt */
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OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
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OUT_RING(ring, 0x00000000);
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/* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
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OUT_PKT3(ring, CP_EVENT_WRITE, 3);
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OUT_RING(ring, CACHE_FLUSH_TS | CP_EVENT_WRITE_0_IRQ);
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OUT_RING(ring, rbmemptr(ring, fence));
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OUT_RING(ring, submit->seqno);
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#if 0
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/* Dummy set-constant to trigger context rollover */
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
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OUT_RING(ring, 0x00000000);
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#endif
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adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);
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}
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static bool a3xx_me_init(struct msm_gpu *gpu)
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{
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struct msm_ringbuffer *ring = gpu->rb[0];
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OUT_PKT3(ring, CP_ME_INIT, 17);
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OUT_RING(ring, 0x000003f7);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000080);
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OUT_RING(ring, 0x00000100);
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OUT_RING(ring, 0x00000180);
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OUT_RING(ring, 0x00006600);
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OUT_RING(ring, 0x00000150);
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OUT_RING(ring, 0x0000014e);
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OUT_RING(ring, 0x00000154);
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OUT_RING(ring, 0x00000001);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);
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return a3xx_idle(gpu);
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}
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static int a3xx_hw_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a3xx_gpu *a3xx_gpu = to_a3xx_gpu(adreno_gpu);
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uint32_t *ptr, len;
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int i, ret;
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DBG("%s", gpu->name);
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if (adreno_is_a305(adreno_gpu)) {
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/* Set up 16 deep read/write request queues: */
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
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gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010);
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/* Enable WR-REQ: */
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gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff);
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/* Set up round robin arbitration between both AXI ports: */
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gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);
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/* Set up AOOO: */
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
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} else if (adreno_is_a306(adreno_gpu)) {
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gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a);
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} else if (adreno_is_a320(adreno_gpu)) {
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/* Set up 16 deep read/write request queues: */
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
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gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010);
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/* Enable WR-REQ: */
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gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff);
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/* Set up round robin arbitration between both AXI ports: */
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gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);
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/* Set up AOOO: */
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
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/* Enable 1K sort: */
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x000000ff);
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
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} else if (adreno_is_a330v2(adreno_gpu)) {
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/*
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* Most of the VBIF registers on 8974v2 have the correct
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* values at power on, so we won't modify those if we don't
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* need to
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*/
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/* Enable 1k sort: */
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
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/* Enable WR-REQ: */
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gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);
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gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
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/* Set up VBIF_ROUND_ROBIN_QOS_ARB: */
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gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
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} else if (adreno_is_a330(adreno_gpu)) {
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/* Set up 16 deep read/write request queues: */
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x18181818);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x18181818);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x18181818);
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gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
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gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);
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gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x18181818);
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/* Enable WR-REQ: */
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gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);
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/* Set up round robin arbitration between both AXI ports: */
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gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);
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/* Set up VBIF_ROUND_ROBIN_QOS_ARB: */
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gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001);
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/* Set up AOOO: */
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003f);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003f003f);
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/* Enable 1K sort: */
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
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/* Disable VBIF clock gating. This is to enable AXI running
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* higher frequency than GPU:
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*/
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gpu_write(gpu, REG_A3XX_VBIF_CLKON, 0x00000001);
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} else {
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BUG();
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}
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/* Make all blocks contribute to the GPU BUSY perf counter: */
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gpu_write(gpu, REG_A3XX_RBBM_GPU_BUSY_MASKED, 0xffffffff);
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/* Tune the hystersis counters for SP and CP idle detection: */
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gpu_write(gpu, REG_A3XX_RBBM_SP_HYST_CNT, 0x10);
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gpu_write(gpu, REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);
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/* Enable the RBBM error reporting bits. This lets us get
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* useful information on failure:
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*/
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gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL0, 0x00000001);
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/* Enable AHB error reporting: */
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gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL1, 0xa6ffffff);
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/* Turn on the power counters: */
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gpu_write(gpu, REG_A3XX_RBBM_RBBM_CTL, 0x00030000);
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/* Turn on hang detection - this spews a lot of useful information
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* into the RBBM registers on a hang:
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*/
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gpu_write(gpu, REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL, 0x00010fff);
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/* Enable 64-byte cacheline size. HW Default is 32-byte (0x000000E0): */
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gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
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/* Enable Clock gating: */
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if (adreno_is_a306(adreno_gpu))
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gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
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else if (adreno_is_a320(adreno_gpu))
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gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
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else if (adreno_is_a330v2(adreno_gpu))
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gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
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else if (adreno_is_a330(adreno_gpu))
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gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbffcffff);
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if (adreno_is_a330v2(adreno_gpu))
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gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x05515455);
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else if (adreno_is_a330(adreno_gpu))
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gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x00000000);
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/* Set the OCMEM base address for A330, etc */
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if (a3xx_gpu->ocmem.hdl) {
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gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR,
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(unsigned int)(a3xx_gpu->ocmem.base >> 14));
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}
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/* Turn on performance counters: */
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gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01);
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/* Enable the perfcntrs that we use.. */
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for (i = 0; i < gpu->num_perfcntrs; i++) {
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const struct msm_gpu_perfcntr *perfcntr = &gpu->perfcntrs[i];
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gpu_write(gpu, perfcntr->select_reg, perfcntr->select_val);
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}
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gpu_write(gpu, REG_A3XX_RBBM_INT_0_MASK, A3XX_INT0_MASK);
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ret = adreno_hw_init(gpu);
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if (ret)
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return ret;
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/*
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* Use the default ringbuffer size and block size but disable the RPTR
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* shadow
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*/
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gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
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MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
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/* Set the ringbuffer address */
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gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));
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/* setup access protection: */
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gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007);
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/* RBBM registers */
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gpu_write(gpu, REG_A3XX_CP_PROTECT(0), 0x63000040);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(1), 0x62000080);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(2), 0x600000cc);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(3), 0x60000108);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(4), 0x64000140);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(5), 0x66000400);
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/* CP registers */
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gpu_write(gpu, REG_A3XX_CP_PROTECT(6), 0x65000700);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(7), 0x610007d8);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(8), 0x620007e0);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(9), 0x61001178);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(10), 0x64001180);
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/* RB registers */
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gpu_write(gpu, REG_A3XX_CP_PROTECT(11), 0x60003300);
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/* VBIF registers */
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gpu_write(gpu, REG_A3XX_CP_PROTECT(12), 0x6b00c000);
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/* NOTE: PM4/micro-engine firmware registers look to be the same
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* for a2xx and a3xx.. we could possibly push that part down to
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* adreno_gpu base class. Or push both PM4 and PFP but
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* parameterize the pfp ucode addr/data registers..
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*/
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/* Load PM4: */
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ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data);
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len = adreno_gpu->fw[ADRENO_FW_PM4]->size / 4;
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DBG("loading PM4 ucode version: %x", ptr[1]);
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gpu_write(gpu, REG_AXXX_CP_DEBUG,
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AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE |
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AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE);
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gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0);
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for (i = 1; i < len; i++)
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gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]);
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/* Load PFP: */
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ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PFP]->data);
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len = adreno_gpu->fw[ADRENO_FW_PFP]->size / 4;
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DBG("loading PFP ucode version: %x", ptr[5]);
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gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0);
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for (i = 1; i < len; i++)
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gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
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/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
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if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) ||
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adreno_is_a320(adreno_gpu)) {
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gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
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AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
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AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
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AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(14));
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} else if (adreno_is_a330(adreno_gpu)) {
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/* NOTE: this (value take from downstream android driver)
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* includes some bits outside of the known bitfields. But
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* A330 has this "MERCIU queue" thing too, which might
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* explain a new bitfield or reshuffling:
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*/
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gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x003e2008);
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}
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/* clear ME_HALT to start micro engine */
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gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);
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return a3xx_me_init(gpu) ? 0 : -EINVAL;
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}
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static void a3xx_recover(struct msm_gpu *gpu)
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{
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int i;
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adreno_dump_info(gpu);
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for (i = 0; i < 8; i++) {
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printk("CP_SCRATCH_REG%d: %u\n", i,
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gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));
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}
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/* dump registers before resetting gpu, if enabled: */
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if (hang_debug)
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a3xx_dump(gpu);
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gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1);
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gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD);
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gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0);
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adreno_recover(gpu);
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}
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static void a3xx_destroy(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a3xx_gpu *a3xx_gpu = to_a3xx_gpu(adreno_gpu);
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DBG("%s", gpu->name);
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adreno_gpu_cleanup(adreno_gpu);
|
|
|
|
adreno_gpu_ocmem_cleanup(&a3xx_gpu->ocmem);
|
|
|
|
kfree(a3xx_gpu);
|
|
}
|
|
|
|
static bool a3xx_idle(struct msm_gpu *gpu)
|
|
{
|
|
/* wait for ringbuffer to drain: */
|
|
if (!adreno_idle(gpu, gpu->rb[0]))
|
|
return false;
|
|
|
|
/* then wait for GPU to finish: */
|
|
if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) &
|
|
A3XX_RBBM_STATUS_GPU_BUSY))) {
|
|
DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name);
|
|
|
|
/* TODO maybe we need to reset GPU here to recover from hang? */
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static irqreturn_t a3xx_irq(struct msm_gpu *gpu)
|
|
{
|
|
uint32_t status;
|
|
|
|
status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS);
|
|
DBG("%s: %08x", gpu->name, status);
|
|
|
|
// TODO
|
|
|
|
gpu_write(gpu, REG_A3XX_RBBM_INT_CLEAR_CMD, status);
|
|
|
|
msm_gpu_retire(gpu);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static const unsigned int a3xx_registers[] = {
|
|
0x0000, 0x0002, 0x0010, 0x0012, 0x0018, 0x0018, 0x0020, 0x0027,
|
|
0x0029, 0x002b, 0x002e, 0x0033, 0x0040, 0x0042, 0x0050, 0x005c,
|
|
0x0060, 0x006c, 0x0080, 0x0082, 0x0084, 0x0088, 0x0090, 0x00e5,
|
|
0x00ea, 0x00ed, 0x0100, 0x0100, 0x0110, 0x0123, 0x01c0, 0x01c1,
|
|
0x01c3, 0x01c5, 0x01c7, 0x01c7, 0x01d5, 0x01d9, 0x01dc, 0x01dd,
|
|
0x01ea, 0x01ea, 0x01ee, 0x01f1, 0x01f5, 0x01f5, 0x01fc, 0x01ff,
|
|
0x0440, 0x0440, 0x0443, 0x0443, 0x0445, 0x0445, 0x044d, 0x044f,
|
|
0x0452, 0x0452, 0x0454, 0x046f, 0x047c, 0x047c, 0x047f, 0x047f,
|
|
0x0578, 0x057f, 0x0600, 0x0602, 0x0605, 0x0607, 0x060a, 0x060e,
|
|
0x0612, 0x0614, 0x0c01, 0x0c02, 0x0c06, 0x0c1d, 0x0c3d, 0x0c3f,
|
|
0x0c48, 0x0c4b, 0x0c80, 0x0c80, 0x0c88, 0x0c8b, 0x0ca0, 0x0cb7,
|
|
0x0cc0, 0x0cc1, 0x0cc6, 0x0cc7, 0x0ce4, 0x0ce5, 0x0e00, 0x0e05,
|
|
0x0e0c, 0x0e0c, 0x0e22, 0x0e23, 0x0e41, 0x0e45, 0x0e64, 0x0e65,
|
|
0x0e80, 0x0e82, 0x0e84, 0x0e89, 0x0ea0, 0x0ea1, 0x0ea4, 0x0ea7,
|
|
0x0ec4, 0x0ecb, 0x0ee0, 0x0ee0, 0x0f00, 0x0f01, 0x0f03, 0x0f09,
|
|
0x2040, 0x2040, 0x2044, 0x2044, 0x2048, 0x204d, 0x2068, 0x2069,
|
|
0x206c, 0x206d, 0x2070, 0x2070, 0x2072, 0x2072, 0x2074, 0x2075,
|
|
0x2079, 0x207a, 0x20c0, 0x20d3, 0x20e4, 0x20ef, 0x2100, 0x2109,
|
|
0x210c, 0x210c, 0x210e, 0x210e, 0x2110, 0x2111, 0x2114, 0x2115,
|
|
0x21e4, 0x21e4, 0x21ea, 0x21ea, 0x21ec, 0x21ed, 0x21f0, 0x21f0,
|
|
0x2200, 0x2212, 0x2214, 0x2217, 0x221a, 0x221a, 0x2240, 0x227e,
|
|
0x2280, 0x228b, 0x22c0, 0x22c0, 0x22c4, 0x22ce, 0x22d0, 0x22d8,
|
|
0x22df, 0x22e6, 0x22e8, 0x22e9, 0x22ec, 0x22ec, 0x22f0, 0x22f7,
|
|
0x22ff, 0x22ff, 0x2340, 0x2343, 0x2440, 0x2440, 0x2444, 0x2444,
|
|
0x2448, 0x244d, 0x2468, 0x2469, 0x246c, 0x246d, 0x2470, 0x2470,
|
|
0x2472, 0x2472, 0x2474, 0x2475, 0x2479, 0x247a, 0x24c0, 0x24d3,
|
|
0x24e4, 0x24ef, 0x2500, 0x2509, 0x250c, 0x250c, 0x250e, 0x250e,
|
|
0x2510, 0x2511, 0x2514, 0x2515, 0x25e4, 0x25e4, 0x25ea, 0x25ea,
|
|
0x25ec, 0x25ed, 0x25f0, 0x25f0, 0x2600, 0x2612, 0x2614, 0x2617,
|
|
0x261a, 0x261a, 0x2640, 0x267e, 0x2680, 0x268b, 0x26c0, 0x26c0,
|
|
0x26c4, 0x26ce, 0x26d0, 0x26d8, 0x26df, 0x26e6, 0x26e8, 0x26e9,
|
|
0x26ec, 0x26ec, 0x26f0, 0x26f7, 0x26ff, 0x26ff, 0x2740, 0x2743,
|
|
0x300c, 0x300e, 0x301c, 0x301d, 0x302a, 0x302a, 0x302c, 0x302d,
|
|
0x3030, 0x3031, 0x3034, 0x3036, 0x303c, 0x303c, 0x305e, 0x305f,
|
|
~0 /* sentinel */
|
|
};
|
|
|
|
/* would be nice to not have to duplicate the _show() stuff with printk(): */
|
|
static void a3xx_dump(struct msm_gpu *gpu)
|
|
{
|
|
printk("status: %08x\n",
|
|
gpu_read(gpu, REG_A3XX_RBBM_STATUS));
|
|
adreno_dump(gpu);
|
|
}
|
|
|
|
static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu)
|
|
{
|
|
struct msm_gpu_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
|
|
|
|
if (!state)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
adreno_gpu_state_get(gpu, state);
|
|
|
|
state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS);
|
|
|
|
return state;
|
|
}
|
|
|
|
static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
|
|
{
|
|
ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR);
|
|
return ring->memptrs->rptr;
|
|
}
|
|
|
|
static const struct adreno_gpu_funcs funcs = {
|
|
.base = {
|
|
.get_param = adreno_get_param,
|
|
.set_param = adreno_set_param,
|
|
.hw_init = a3xx_hw_init,
|
|
.pm_suspend = msm_gpu_pm_suspend,
|
|
.pm_resume = msm_gpu_pm_resume,
|
|
.recover = a3xx_recover,
|
|
.submit = a3xx_submit,
|
|
.active_ring = adreno_active_ring,
|
|
.irq = a3xx_irq,
|
|
.destroy = a3xx_destroy,
|
|
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
|
|
.show = adreno_show,
|
|
#endif
|
|
.gpu_state_get = a3xx_gpu_state_get,
|
|
.gpu_state_put = adreno_gpu_state_put,
|
|
.create_address_space = adreno_create_address_space,
|
|
.get_rptr = a3xx_get_rptr,
|
|
},
|
|
};
|
|
|
|
static const struct msm_gpu_perfcntr perfcntrs[] = {
|
|
{ REG_A3XX_SP_PERFCOUNTER6_SELECT, REG_A3XX_RBBM_PERFCTR_SP_6_LO,
|
|
SP_ALU_ACTIVE_CYCLES, "ALUACTIVE" },
|
|
{ REG_A3XX_SP_PERFCOUNTER7_SELECT, REG_A3XX_RBBM_PERFCTR_SP_7_LO,
|
|
SP_FS_FULL_ALU_INSTRUCTIONS, "ALUFULL" },
|
|
};
|
|
|
|
struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
|
|
{
|
|
struct a3xx_gpu *a3xx_gpu = NULL;
|
|
struct adreno_gpu *adreno_gpu;
|
|
struct msm_gpu *gpu;
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
struct platform_device *pdev = priv->gpu_pdev;
|
|
struct icc_path *ocmem_icc_path;
|
|
struct icc_path *icc_path;
|
|
int ret;
|
|
|
|
if (!pdev) {
|
|
DRM_DEV_ERROR(dev->dev, "no a3xx device\n");
|
|
ret = -ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
a3xx_gpu = kzalloc(sizeof(*a3xx_gpu), GFP_KERNEL);
|
|
if (!a3xx_gpu) {
|
|
ret = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
|
|
adreno_gpu = &a3xx_gpu->base;
|
|
gpu = &adreno_gpu->base;
|
|
|
|
gpu->perfcntrs = perfcntrs;
|
|
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
|
|
|
|
adreno_gpu->registers = a3xx_registers;
|
|
|
|
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
/* if needed, allocate gmem: */
|
|
if (adreno_is_a330(adreno_gpu)) {
|
|
ret = adreno_gpu_ocmem_init(&adreno_gpu->base.pdev->dev,
|
|
adreno_gpu, &a3xx_gpu->ocmem);
|
|
if (ret)
|
|
goto fail;
|
|
}
|
|
|
|
if (!gpu->aspace) {
|
|
/* TODO we think it is possible to configure the GPU to
|
|
* restrict access to VRAM carveout. But the required
|
|
* registers are unknown. For now just bail out and
|
|
* limp along with just modesetting. If it turns out
|
|
* to not be possible to restrict access, then we must
|
|
* implement a cmdstream validator.
|
|
*/
|
|
DRM_DEV_ERROR(dev->dev, "No memory protection without IOMMU\n");
|
|
if (!allow_vram_carveout) {
|
|
ret = -ENXIO;
|
|
goto fail;
|
|
}
|
|
}
|
|
|
|
icc_path = devm_of_icc_get(&pdev->dev, "gfx-mem");
|
|
if (IS_ERR(icc_path)) {
|
|
ret = PTR_ERR(icc_path);
|
|
goto fail;
|
|
}
|
|
|
|
ocmem_icc_path = devm_of_icc_get(&pdev->dev, "ocmem");
|
|
if (IS_ERR(ocmem_icc_path)) {
|
|
ret = PTR_ERR(ocmem_icc_path);
|
|
/* allow -ENODATA, ocmem icc is optional */
|
|
if (ret != -ENODATA)
|
|
goto fail;
|
|
ocmem_icc_path = NULL;
|
|
}
|
|
|
|
|
|
/*
|
|
* Set the ICC path to maximum speed for now by multiplying the fastest
|
|
* frequency by the bus width (8). We'll want to scale this later on to
|
|
* improve battery life.
|
|
*/
|
|
icc_set_bw(icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);
|
|
icc_set_bw(ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);
|
|
|
|
return gpu;
|
|
|
|
fail:
|
|
if (a3xx_gpu)
|
|
a3xx_destroy(&a3xx_gpu->base.base);
|
|
|
|
return ERR_PTR(ret);
|
|
}
|