747 lines
18 KiB
C
747 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013-2014 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
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*/
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#include "adreno_gpu.h"
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bool hang_debug = false;
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MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
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module_param_named(hang_debug, hang_debug, bool, 0600);
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bool snapshot_debugbus = false;
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MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
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module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
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bool allow_vram_carveout = false;
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MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
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module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
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static const struct adreno_info gpulist[] = {
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{
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.rev = ADRENO_REV(2, 0, 0, 0),
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.revn = 200,
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.name = "A200",
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.fw = {
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[ADRENO_FW_PM4] = "yamato_pm4.fw",
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[ADRENO_FW_PFP] = "yamato_pfp.fw",
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},
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.gmem = SZ_256K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a2xx_gpu_init,
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}, { /* a200 on i.mx51 has only 128kib gmem */
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.rev = ADRENO_REV(2, 0, 0, 1),
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.revn = 201,
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.name = "A200",
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.fw = {
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[ADRENO_FW_PM4] = "yamato_pm4.fw",
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[ADRENO_FW_PFP] = "yamato_pfp.fw",
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},
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.gmem = SZ_128K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a2xx_gpu_init,
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}, {
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.rev = ADRENO_REV(2, 2, 0, ANY_ID),
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.revn = 220,
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.name = "A220",
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.fw = {
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[ADRENO_FW_PM4] = "leia_pm4_470.fw",
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[ADRENO_FW_PFP] = "leia_pfp_470.fw",
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},
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.gmem = SZ_512K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a2xx_gpu_init,
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}, {
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.rev = ADRENO_REV(3, 0, 5, ANY_ID),
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.revn = 305,
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.name = "A305",
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.fw = {
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[ADRENO_FW_PM4] = "a300_pm4.fw",
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[ADRENO_FW_PFP] = "a300_pfp.fw",
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},
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.gmem = SZ_256K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a3xx_gpu_init,
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}, {
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.rev = ADRENO_REV(3, 0, 6, 0),
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.revn = 307, /* because a305c is revn==306 */
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.name = "A306",
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.fw = {
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[ADRENO_FW_PM4] = "a300_pm4.fw",
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[ADRENO_FW_PFP] = "a300_pfp.fw",
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},
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.gmem = SZ_128K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a3xx_gpu_init,
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}, {
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.rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
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.revn = 320,
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.name = "A320",
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.fw = {
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[ADRENO_FW_PM4] = "a300_pm4.fw",
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[ADRENO_FW_PFP] = "a300_pfp.fw",
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},
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.gmem = SZ_512K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a3xx_gpu_init,
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}, {
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.rev = ADRENO_REV(3, 3, 0, ANY_ID),
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.revn = 330,
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.name = "A330",
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.fw = {
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[ADRENO_FW_PM4] = "a330_pm4.fw",
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[ADRENO_FW_PFP] = "a330_pfp.fw",
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},
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.gmem = SZ_1M,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a3xx_gpu_init,
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}, {
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.rev = ADRENO_REV(4, 0, 5, ANY_ID),
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.revn = 405,
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.name = "A405",
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.fw = {
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[ADRENO_FW_PM4] = "a420_pm4.fw",
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[ADRENO_FW_PFP] = "a420_pfp.fw",
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},
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.gmem = SZ_256K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a4xx_gpu_init,
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}, {
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.rev = ADRENO_REV(4, 2, 0, ANY_ID),
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.revn = 420,
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.name = "A420",
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.fw = {
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[ADRENO_FW_PM4] = "a420_pm4.fw",
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[ADRENO_FW_PFP] = "a420_pfp.fw",
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},
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.gmem = (SZ_1M + SZ_512K),
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a4xx_gpu_init,
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}, {
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.rev = ADRENO_REV(4, 3, 0, ANY_ID),
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.revn = 430,
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.name = "A430",
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.fw = {
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[ADRENO_FW_PM4] = "a420_pm4.fw",
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[ADRENO_FW_PFP] = "a420_pfp.fw",
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},
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.gmem = (SZ_1M + SZ_512K),
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a4xx_gpu_init,
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}, {
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.rev = ADRENO_REV(5, 0, 6, ANY_ID),
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.revn = 506,
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.name = "A506",
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.fw = {
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[ADRENO_FW_PM4] = "a530_pm4.fw",
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[ADRENO_FW_PFP] = "a530_pfp.fw",
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},
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.gmem = (SZ_128K + SZ_8K),
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/*
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* Increase inactive period to 250 to avoid bouncing
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* the GDSC which appears to make it grumpy
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*/
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.inactive_period = 250,
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.quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
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ADRENO_QUIRK_LMLOADKILL_DISABLE,
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.init = a5xx_gpu_init,
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.zapfw = "a506_zap.mdt",
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}, {
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.rev = ADRENO_REV(5, 0, 8, ANY_ID),
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.revn = 508,
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.name = "A508",
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.fw = {
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[ADRENO_FW_PM4] = "a530_pm4.fw",
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[ADRENO_FW_PFP] = "a530_pfp.fw",
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},
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.gmem = (SZ_128K + SZ_8K),
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/*
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* Increase inactive period to 250 to avoid bouncing
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* the GDSC which appears to make it grumpy
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*/
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.inactive_period = 250,
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.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
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.init = a5xx_gpu_init,
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.zapfw = "a508_zap.mdt",
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}, {
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.rev = ADRENO_REV(5, 0, 9, ANY_ID),
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.revn = 509,
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.name = "A509",
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.fw = {
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[ADRENO_FW_PM4] = "a530_pm4.fw",
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[ADRENO_FW_PFP] = "a530_pfp.fw",
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},
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.gmem = (SZ_256K + SZ_16K),
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/*
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* Increase inactive period to 250 to avoid bouncing
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* the GDSC which appears to make it grumpy
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*/
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.inactive_period = 250,
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.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
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.init = a5xx_gpu_init,
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/* Adreno 509 uses the same ZAP as 512 */
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.zapfw = "a512_zap.mdt",
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}, {
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.rev = ADRENO_REV(5, 1, 0, ANY_ID),
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.revn = 510,
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.name = "A510",
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.fw = {
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[ADRENO_FW_PM4] = "a530_pm4.fw",
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[ADRENO_FW_PFP] = "a530_pfp.fw",
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},
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.gmem = SZ_256K,
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/*
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* Increase inactive period to 250 to avoid bouncing
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* the GDSC which appears to make it grumpy
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*/
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.inactive_period = 250,
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.init = a5xx_gpu_init,
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}, {
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.rev = ADRENO_REV(5, 1, 2, ANY_ID),
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.revn = 512,
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.name = "A512",
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.fw = {
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[ADRENO_FW_PM4] = "a530_pm4.fw",
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[ADRENO_FW_PFP] = "a530_pfp.fw",
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},
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.gmem = (SZ_256K + SZ_16K),
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/*
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* Increase inactive period to 250 to avoid bouncing
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* the GDSC which appears to make it grumpy
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*/
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.inactive_period = 250,
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.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
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.init = a5xx_gpu_init,
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.zapfw = "a512_zap.mdt",
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}, {
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.rev = ADRENO_REV(5, 3, 0, 2),
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.revn = 530,
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.name = "A530",
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.fw = {
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[ADRENO_FW_PM4] = "a530_pm4.fw",
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[ADRENO_FW_PFP] = "a530_pfp.fw",
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[ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
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},
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.gmem = SZ_1M,
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/*
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* Increase inactive period to 250 to avoid bouncing
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* the GDSC which appears to make it grumpy
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*/
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.inactive_period = 250,
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.quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
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ADRENO_QUIRK_FAULT_DETECT_MASK,
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.init = a5xx_gpu_init,
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.zapfw = "a530_zap.mdt",
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}, {
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.rev = ADRENO_REV(5, 4, 0, ANY_ID),
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.revn = 540,
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.name = "A540",
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.fw = {
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[ADRENO_FW_PM4] = "a530_pm4.fw",
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[ADRENO_FW_PFP] = "a530_pfp.fw",
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[ADRENO_FW_GPMU] = "a540_gpmu.fw2",
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},
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.gmem = SZ_1M,
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/*
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* Increase inactive period to 250 to avoid bouncing
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* the GDSC which appears to make it grumpy
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*/
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.inactive_period = 250,
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.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
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.init = a5xx_gpu_init,
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.zapfw = "a540_zap.mdt",
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}, {
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.rev = ADRENO_REV(6, 1, 8, ANY_ID),
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.revn = 618,
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.name = "A618",
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.fw = {
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[ADRENO_FW_SQE] = "a630_sqe.fw",
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[ADRENO_FW_GMU] = "a630_gmu.bin",
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},
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.gmem = SZ_512K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a6xx_gpu_init,
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}, {
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.rev = ADRENO_REV(6, 1, 9, ANY_ID),
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.revn = 619,
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.name = "A619",
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.fw = {
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[ADRENO_FW_SQE] = "a630_sqe.fw",
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[ADRENO_FW_GMU] = "a619_gmu.bin",
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},
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.gmem = SZ_512K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a6xx_gpu_init,
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.zapfw = "a615_zap.mdt",
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.hwcg = a615_hwcg,
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}, {
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.rev = ADRENO_REV(6, 3, 0, ANY_ID),
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.revn = 630,
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.name = "A630",
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.fw = {
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[ADRENO_FW_SQE] = "a630_sqe.fw",
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[ADRENO_FW_GMU] = "a630_gmu.bin",
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},
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.gmem = SZ_1M,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a6xx_gpu_init,
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.zapfw = "a630_zap.mdt",
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.hwcg = a630_hwcg,
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}, {
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.rev = ADRENO_REV(6, 4, 0, ANY_ID),
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.revn = 640,
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.name = "A640",
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.fw = {
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[ADRENO_FW_SQE] = "a630_sqe.fw",
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[ADRENO_FW_GMU] = "a640_gmu.bin",
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},
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.gmem = SZ_1M,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a6xx_gpu_init,
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.zapfw = "a640_zap.mdt",
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.hwcg = a640_hwcg,
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}, {
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.rev = ADRENO_REV(6, 5, 0, ANY_ID),
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.revn = 650,
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.name = "A650",
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.fw = {
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[ADRENO_FW_SQE] = "a650_sqe.fw",
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[ADRENO_FW_GMU] = "a650_gmu.bin",
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},
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.gmem = SZ_1M + SZ_128K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a6xx_gpu_init,
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.zapfw = "a650_zap.mdt",
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.hwcg = a650_hwcg,
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.address_space_size = SZ_16G,
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}, {
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.rev = ADRENO_REV(6, 6, 0, ANY_ID),
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.revn = 660,
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.name = "A660",
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.fw = {
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[ADRENO_FW_SQE] = "a660_sqe.fw",
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[ADRENO_FW_GMU] = "a660_gmu.bin",
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},
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.gmem = SZ_1M + SZ_512K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a6xx_gpu_init,
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.zapfw = "a660_zap.mdt",
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.hwcg = a660_hwcg,
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.address_space_size = SZ_16G,
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}, {
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.rev = ADRENO_REV(6, 3, 5, ANY_ID),
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.fw = {
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[ADRENO_FW_SQE] = "a660_sqe.fw",
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[ADRENO_FW_GMU] = "a660_gmu.bin",
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},
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.gmem = SZ_512K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a6xx_gpu_init,
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.hwcg = a660_hwcg,
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.address_space_size = SZ_16G,
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}, {
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.rev = ADRENO_REV(6, 8, 0, ANY_ID),
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.revn = 680,
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.name = "A680",
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.fw = {
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[ADRENO_FW_SQE] = "a630_sqe.fw",
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[ADRENO_FW_GMU] = "a640_gmu.bin",
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},
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.gmem = SZ_2M,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a6xx_gpu_init,
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.zapfw = "a640_zap.mdt",
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.hwcg = a640_hwcg,
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},
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};
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MODULE_FIRMWARE("qcom/a300_pm4.fw");
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MODULE_FIRMWARE("qcom/a300_pfp.fw");
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MODULE_FIRMWARE("qcom/a330_pm4.fw");
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MODULE_FIRMWARE("qcom/a330_pfp.fw");
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MODULE_FIRMWARE("qcom/a420_pm4.fw");
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MODULE_FIRMWARE("qcom/a420_pfp.fw");
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MODULE_FIRMWARE("qcom/a530_pm4.fw");
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MODULE_FIRMWARE("qcom/a530_pfp.fw");
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MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
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MODULE_FIRMWARE("qcom/a530_zap.mdt");
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MODULE_FIRMWARE("qcom/a530_zap.b00");
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MODULE_FIRMWARE("qcom/a530_zap.b01");
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MODULE_FIRMWARE("qcom/a530_zap.b02");
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MODULE_FIRMWARE("qcom/a619_gmu.bin");
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MODULE_FIRMWARE("qcom/a630_sqe.fw");
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MODULE_FIRMWARE("qcom/a630_gmu.bin");
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MODULE_FIRMWARE("qcom/a630_zap.mbn");
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static inline bool _rev_match(uint8_t entry, uint8_t id)
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{
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return (entry == ANY_ID) || (entry == id);
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}
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bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)
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{
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return _rev_match(rev1.core, rev2.core) &&
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_rev_match(rev1.major, rev2.major) &&
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_rev_match(rev1.minor, rev2.minor) &&
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_rev_match(rev1.patchid, rev2.patchid);
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}
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const struct adreno_info *adreno_info(struct adreno_rev rev)
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{
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int i;
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/* identify gpu: */
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for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
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const struct adreno_info *info = &gpulist[i];
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if (adreno_cmp_rev(info->rev, rev))
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return info;
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}
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return NULL;
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}
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struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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struct platform_device *pdev = priv->gpu_pdev;
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struct msm_gpu *gpu = NULL;
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struct adreno_gpu *adreno_gpu;
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int ret;
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if (pdev)
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gpu = dev_to_gpu(&pdev->dev);
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if (!gpu) {
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dev_err_once(dev->dev, "no GPU device was found\n");
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return NULL;
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}
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adreno_gpu = to_adreno_gpu(gpu);
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/*
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* The number one reason for HW init to fail is if the firmware isn't
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* loaded yet. Try that first and don't bother continuing on
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* otherwise
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*/
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ret = adreno_load_fw(adreno_gpu);
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if (ret)
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return NULL;
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/*
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* Now that we have firmware loaded, and are ready to begin
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* booting the gpu, go ahead and enable runpm:
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*/
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pm_runtime_enable(&pdev->dev);
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|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
|
if (ret < 0) {
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
|
|
goto err_disable_rpm;
|
|
}
|
|
|
|
mutex_lock(&gpu->lock);
|
|
ret = msm_gpu_hw_init(gpu);
|
|
mutex_unlock(&gpu->lock);
|
|
if (ret) {
|
|
DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
|
|
goto err_put_rpm;
|
|
}
|
|
|
|
pm_runtime_put_autosuspend(&pdev->dev);
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
if (gpu->funcs->debugfs_init) {
|
|
gpu->funcs->debugfs_init(gpu, dev->primary);
|
|
gpu->funcs->debugfs_init(gpu, dev->render);
|
|
}
|
|
#endif
|
|
|
|
return gpu;
|
|
|
|
err_put_rpm:
|
|
pm_runtime_put_sync_suspend(&pdev->dev);
|
|
err_disable_rpm:
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static int find_chipid(struct device *dev, struct adreno_rev *rev)
|
|
{
|
|
struct device_node *node = dev->of_node;
|
|
const char *compat;
|
|
int ret;
|
|
u32 chipid;
|
|
|
|
/* first search the compat strings for qcom,adreno-XYZ.W: */
|
|
ret = of_property_read_string_index(node, "compatible", 0, &compat);
|
|
if (ret == 0) {
|
|
unsigned int r, patch;
|
|
|
|
if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
|
|
sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
|
|
rev->core = r / 100;
|
|
r %= 100;
|
|
rev->major = r / 10;
|
|
r %= 10;
|
|
rev->minor = r;
|
|
rev->patchid = patch;
|
|
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* and if that fails, fall back to legacy "qcom,chipid" property: */
|
|
ret = of_property_read_u32(node, "qcom,chipid", &chipid);
|
|
if (ret) {
|
|
DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
rev->core = (chipid >> 24) & 0xff;
|
|
rev->major = (chipid >> 16) & 0xff;
|
|
rev->minor = (chipid >> 8) & 0xff;
|
|
rev->patchid = (chipid & 0xff);
|
|
|
|
dev_warn(dev, "Using legacy qcom,chipid binding!\n");
|
|
dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
|
|
rev->core, rev->major, rev->minor, rev->patchid);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int adreno_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
static struct adreno_platform_config config = {};
|
|
const struct adreno_info *info;
|
|
struct msm_drm_private *priv = dev_get_drvdata(master);
|
|
struct drm_device *drm = priv->dev;
|
|
struct msm_gpu *gpu;
|
|
int ret;
|
|
|
|
ret = find_chipid(dev, &config.rev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dev->platform_data = &config;
|
|
priv->gpu_pdev = to_platform_device(dev);
|
|
|
|
info = adreno_info(config.rev);
|
|
|
|
if (!info) {
|
|
dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
|
|
config.rev.core, config.rev.major,
|
|
config.rev.minor, config.rev.patchid);
|
|
return -ENXIO;
|
|
}
|
|
|
|
DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
|
|
config.rev.minor, config.rev.patchid);
|
|
|
|
priv->is_a2xx = config.rev.core == 2;
|
|
priv->has_cached_coherent = config.rev.core >= 6;
|
|
|
|
gpu = info->init(drm);
|
|
if (IS_ERR(gpu)) {
|
|
dev_warn(drm->dev, "failed to load adreno gpu\n");
|
|
return PTR_ERR(gpu);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int adreno_system_suspend(struct device *dev);
|
|
static void adreno_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct msm_drm_private *priv = dev_get_drvdata(master);
|
|
struct msm_gpu *gpu = dev_to_gpu(dev);
|
|
|
|
if (pm_runtime_enabled(dev))
|
|
WARN_ON_ONCE(adreno_system_suspend(dev));
|
|
gpu->funcs->destroy(gpu);
|
|
|
|
priv->gpu_pdev = NULL;
|
|
}
|
|
|
|
static const struct component_ops a3xx_ops = {
|
|
.bind = adreno_bind,
|
|
.unbind = adreno_unbind,
|
|
};
|
|
|
|
static void adreno_device_register_headless(void)
|
|
{
|
|
/* on imx5, we don't have a top-level mdp/dpu node
|
|
* this creates a dummy node for the driver for that case
|
|
*/
|
|
struct platform_device_info dummy_info = {
|
|
.parent = NULL,
|
|
.name = "msm",
|
|
.id = -1,
|
|
.res = NULL,
|
|
.num_res = 0,
|
|
.data = NULL,
|
|
.size_data = 0,
|
|
.dma_mask = ~0,
|
|
};
|
|
platform_device_register_full(&dummy_info);
|
|
}
|
|
|
|
static int adreno_probe(struct platform_device *pdev)
|
|
{
|
|
|
|
int ret;
|
|
|
|
ret = component_add(&pdev->dev, &a3xx_ops);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
|
|
adreno_device_register_headless();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int adreno_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &a3xx_ops);
|
|
return 0;
|
|
}
|
|
|
|
static void adreno_shutdown(struct platform_device *pdev)
|
|
{
|
|
WARN_ON_ONCE(adreno_system_suspend(&pdev->dev));
|
|
}
|
|
|
|
static const struct of_device_id dt_match[] = {
|
|
{ .compatible = "qcom,adreno" },
|
|
{ .compatible = "qcom,adreno-3xx" },
|
|
/* for compatibility with imx5 gpu: */
|
|
{ .compatible = "amd,imageon" },
|
|
/* for backwards compat w/ downstream kgsl DT files: */
|
|
{ .compatible = "qcom,kgsl-3d0" },
|
|
{}
|
|
};
|
|
|
|
static int adreno_runtime_resume(struct device *dev)
|
|
{
|
|
struct msm_gpu *gpu = dev_to_gpu(dev);
|
|
|
|
return gpu->funcs->pm_resume(gpu);
|
|
}
|
|
|
|
static int adreno_runtime_suspend(struct device *dev)
|
|
{
|
|
struct msm_gpu *gpu = dev_to_gpu(dev);
|
|
|
|
/*
|
|
* We should be holding a runpm ref, which will prevent
|
|
* runtime suspend. In the system suspend path, we've
|
|
* already waited for active jobs to complete.
|
|
*/
|
|
WARN_ON_ONCE(gpu->active_submits);
|
|
|
|
return gpu->funcs->pm_suspend(gpu);
|
|
}
|
|
|
|
static void suspend_scheduler(struct msm_gpu *gpu)
|
|
{
|
|
int i;
|
|
|
|
/*
|
|
* Shut down the scheduler before we force suspend, so that
|
|
* suspend isn't racing with scheduler kthread feeding us
|
|
* more work.
|
|
*
|
|
* Note, we just want to park the thread, and let any jobs
|
|
* that are already on the hw queue complete normally, as
|
|
* opposed to the drm_sched_stop() path used for handling
|
|
* faulting/timed-out jobs. We can't really cancel any jobs
|
|
* already on the hw queue without racing with the GPU.
|
|
*/
|
|
for (i = 0; i < gpu->nr_rings; i++) {
|
|
struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;
|
|
kthread_park(sched->thread);
|
|
}
|
|
}
|
|
|
|
static void resume_scheduler(struct msm_gpu *gpu)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < gpu->nr_rings; i++) {
|
|
struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;
|
|
kthread_unpark(sched->thread);
|
|
}
|
|
}
|
|
|
|
static int adreno_system_suspend(struct device *dev)
|
|
{
|
|
struct msm_gpu *gpu = dev_to_gpu(dev);
|
|
int remaining, ret;
|
|
|
|
if (!gpu)
|
|
return 0;
|
|
|
|
suspend_scheduler(gpu);
|
|
|
|
remaining = wait_event_timeout(gpu->retire_event,
|
|
gpu->active_submits == 0,
|
|
msecs_to_jiffies(1000));
|
|
if (remaining == 0) {
|
|
dev_err(dev, "Timeout waiting for GPU to suspend\n");
|
|
ret = -EBUSY;
|
|
goto out;
|
|
}
|
|
|
|
ret = pm_runtime_force_suspend(dev);
|
|
out:
|
|
if (ret)
|
|
resume_scheduler(gpu);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int adreno_system_resume(struct device *dev)
|
|
{
|
|
struct msm_gpu *gpu = dev_to_gpu(dev);
|
|
|
|
if (!gpu)
|
|
return 0;
|
|
|
|
resume_scheduler(gpu);
|
|
return pm_runtime_force_resume(dev);
|
|
}
|
|
|
|
static const struct dev_pm_ops adreno_pm_ops = {
|
|
SYSTEM_SLEEP_PM_OPS(adreno_system_suspend, adreno_system_resume)
|
|
RUNTIME_PM_OPS(adreno_runtime_suspend, adreno_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver adreno_driver = {
|
|
.probe = adreno_probe,
|
|
.remove = adreno_remove,
|
|
.shutdown = adreno_shutdown,
|
|
.driver = {
|
|
.name = "adreno",
|
|
.of_match_table = dt_match,
|
|
.pm = &adreno_pm_ops,
|
|
},
|
|
};
|
|
|
|
void __init adreno_register(void)
|
|
{
|
|
platform_driver_register(&adreno_driver);
|
|
}
|
|
|
|
void __exit adreno_unregister(void)
|
|
{
|
|
platform_driver_unregister(&adreno_driver);
|
|
}
|