255 lines
7.7 KiB
C
255 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#include <linux/hdmi.h>
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#include "hdmi.h"
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/* maps MSM_HDMI_AUDIO_CHANNEL_n consts used by audio driver to # of channels: */
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static int nchannels[] = { 2, 4, 6, 8 };
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/* Supported HDMI Audio sample rates */
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#define MSM_HDMI_SAMPLE_RATE_32KHZ 0
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#define MSM_HDMI_SAMPLE_RATE_44_1KHZ 1
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#define MSM_HDMI_SAMPLE_RATE_48KHZ 2
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#define MSM_HDMI_SAMPLE_RATE_88_2KHZ 3
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#define MSM_HDMI_SAMPLE_RATE_96KHZ 4
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#define MSM_HDMI_SAMPLE_RATE_176_4KHZ 5
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#define MSM_HDMI_SAMPLE_RATE_192KHZ 6
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#define MSM_HDMI_SAMPLE_RATE_MAX 7
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struct hdmi_msm_audio_acr {
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uint32_t n; /* N parameter for clock regeneration */
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uint32_t cts; /* CTS parameter for clock regeneration */
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};
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struct hdmi_msm_audio_arcs {
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unsigned long int pixclock;
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struct hdmi_msm_audio_acr lut[MSM_HDMI_SAMPLE_RATE_MAX];
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};
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#define HDMI_MSM_AUDIO_ARCS(pclk, ...) { (1000 * (pclk)), __VA_ARGS__ }
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/* Audio constants lookup table for hdmi_msm_audio_acr_setup */
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/* Valid Pixel-Clock rates: 25.2MHz, 27MHz, 27.03MHz, 74.25MHz, 148.5MHz */
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static const struct hdmi_msm_audio_arcs acr_lut[] = {
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/* 25.200MHz */
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HDMI_MSM_AUDIO_ARCS(25200, {
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{4096, 25200}, {6272, 28000}, {6144, 25200}, {12544, 28000},
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{12288, 25200}, {25088, 28000}, {24576, 25200} }),
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/* 27.000MHz */
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HDMI_MSM_AUDIO_ARCS(27000, {
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{4096, 27000}, {6272, 30000}, {6144, 27000}, {12544, 30000},
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{12288, 27000}, {25088, 30000}, {24576, 27000} }),
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/* 27.027MHz */
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HDMI_MSM_AUDIO_ARCS(27030, {
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{4096, 27027}, {6272, 30030}, {6144, 27027}, {12544, 30030},
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{12288, 27027}, {25088, 30030}, {24576, 27027} }),
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/* 74.250MHz */
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HDMI_MSM_AUDIO_ARCS(74250, {
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{4096, 74250}, {6272, 82500}, {6144, 74250}, {12544, 82500},
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{12288, 74250}, {25088, 82500}, {24576, 74250} }),
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/* 148.500MHz */
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HDMI_MSM_AUDIO_ARCS(148500, {
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{4096, 148500}, {6272, 165000}, {6144, 148500}, {12544, 165000},
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{12288, 148500}, {25088, 165000}, {24576, 148500} }),
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};
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static const struct hdmi_msm_audio_arcs *get_arcs(unsigned long int pixclock)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(acr_lut); i++) {
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const struct hdmi_msm_audio_arcs *arcs = &acr_lut[i];
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if (arcs->pixclock == pixclock)
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return arcs;
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}
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return NULL;
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}
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int msm_hdmi_audio_update(struct hdmi *hdmi)
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{
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struct hdmi_audio *audio = &hdmi->audio;
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struct hdmi_audio_infoframe *info = &audio->infoframe;
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const struct hdmi_msm_audio_arcs *arcs = NULL;
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bool enabled = audio->enabled;
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uint32_t acr_pkt_ctrl, vbi_pkt_ctrl, aud_pkt_ctrl;
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uint32_t infofrm_ctrl, audio_config;
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DBG("audio: enabled=%d, channels=%d, channel_allocation=0x%x, "
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"level_shift_value=%d, downmix_inhibit=%d, rate=%d",
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audio->enabled, info->channels, info->channel_allocation,
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info->level_shift_value, info->downmix_inhibit, audio->rate);
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DBG("video: power_on=%d, pixclock=%lu", hdmi->power_on, hdmi->pixclock);
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if (enabled && !(hdmi->power_on && hdmi->pixclock)) {
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DBG("disabling audio: no video");
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enabled = false;
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}
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if (enabled) {
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arcs = get_arcs(hdmi->pixclock);
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if (!arcs) {
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DBG("disabling audio: unsupported pixclock: %lu",
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hdmi->pixclock);
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enabled = false;
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}
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}
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/* Read first before writing */
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acr_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_ACR_PKT_CTRL);
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vbi_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_VBI_PKT_CTRL);
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aud_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_AUDIO_PKT_CTRL1);
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infofrm_ctrl = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL0);
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audio_config = hdmi_read(hdmi, REG_HDMI_AUDIO_CFG);
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/* Clear N/CTS selection bits */
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acr_pkt_ctrl &= ~HDMI_ACR_PKT_CTRL_SELECT__MASK;
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if (enabled) {
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uint32_t n, cts, multiplier;
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enum hdmi_acr_cts select;
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uint8_t buf[14];
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n = arcs->lut[audio->rate].n;
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cts = arcs->lut[audio->rate].cts;
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if ((MSM_HDMI_SAMPLE_RATE_192KHZ == audio->rate) ||
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(MSM_HDMI_SAMPLE_RATE_176_4KHZ == audio->rate)) {
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multiplier = 4;
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n >>= 2; /* divide N by 4 and use multiplier */
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} else if ((MSM_HDMI_SAMPLE_RATE_96KHZ == audio->rate) ||
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(MSM_HDMI_SAMPLE_RATE_88_2KHZ == audio->rate)) {
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multiplier = 2;
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n >>= 1; /* divide N by 2 and use multiplier */
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} else {
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multiplier = 1;
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}
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DBG("n=%u, cts=%u, multiplier=%u", n, cts, multiplier);
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acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_SOURCE;
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acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY;
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acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_N_MULTIPLIER(multiplier);
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if ((MSM_HDMI_SAMPLE_RATE_48KHZ == audio->rate) ||
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(MSM_HDMI_SAMPLE_RATE_96KHZ == audio->rate) ||
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(MSM_HDMI_SAMPLE_RATE_192KHZ == audio->rate))
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select = ACR_48;
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else if ((MSM_HDMI_SAMPLE_RATE_44_1KHZ == audio->rate) ||
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(MSM_HDMI_SAMPLE_RATE_88_2KHZ == audio->rate) ||
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(MSM_HDMI_SAMPLE_RATE_176_4KHZ == audio->rate))
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select = ACR_44;
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else /* default to 32k */
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select = ACR_32;
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acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_SELECT(select);
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hdmi_write(hdmi, REG_HDMI_ACR_0(select - 1),
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HDMI_ACR_0_CTS(cts));
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hdmi_write(hdmi, REG_HDMI_ACR_1(select - 1),
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HDMI_ACR_1_N(n));
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hdmi_write(hdmi, REG_HDMI_AUDIO_PKT_CTRL2,
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COND(info->channels != 2, HDMI_AUDIO_PKT_CTRL2_LAYOUT) |
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HDMI_AUDIO_PKT_CTRL2_OVERRIDE);
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acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_CONT;
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acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_SEND;
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/* configure infoframe: */
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hdmi_audio_infoframe_pack(info, buf, sizeof(buf));
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hdmi_write(hdmi, REG_HDMI_AUDIO_INFO0,
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(buf[3] << 0) | (buf[4] << 8) |
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(buf[5] << 16) | (buf[6] << 24));
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hdmi_write(hdmi, REG_HDMI_AUDIO_INFO1,
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(buf[7] << 0) | (buf[8] << 8));
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hdmi_write(hdmi, REG_HDMI_GC, 0);
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vbi_pkt_ctrl |= HDMI_VBI_PKT_CTRL_GC_ENABLE;
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vbi_pkt_ctrl |= HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME;
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aud_pkt_ctrl |= HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND;
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infofrm_ctrl |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND;
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infofrm_ctrl |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT;
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infofrm_ctrl |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE;
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infofrm_ctrl |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE;
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audio_config &= ~HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK;
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audio_config |= HDMI_AUDIO_CFG_FIFO_WATERMARK(4);
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audio_config |= HDMI_AUDIO_CFG_ENGINE_ENABLE;
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} else {
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acr_pkt_ctrl &= ~HDMI_ACR_PKT_CTRL_CONT;
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acr_pkt_ctrl &= ~HDMI_ACR_PKT_CTRL_SEND;
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vbi_pkt_ctrl &= ~HDMI_VBI_PKT_CTRL_GC_ENABLE;
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vbi_pkt_ctrl &= ~HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME;
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aud_pkt_ctrl &= ~HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND;
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infofrm_ctrl &= ~HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND;
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infofrm_ctrl &= ~HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT;
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infofrm_ctrl &= ~HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE;
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infofrm_ctrl &= ~HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE;
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audio_config &= ~HDMI_AUDIO_CFG_ENGINE_ENABLE;
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}
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hdmi_write(hdmi, REG_HDMI_ACR_PKT_CTRL, acr_pkt_ctrl);
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hdmi_write(hdmi, REG_HDMI_VBI_PKT_CTRL, vbi_pkt_ctrl);
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hdmi_write(hdmi, REG_HDMI_AUDIO_PKT_CTRL1, aud_pkt_ctrl);
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hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0, infofrm_ctrl);
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hdmi_write(hdmi, REG_HDMI_AUD_INT,
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COND(enabled, HDMI_AUD_INT_AUD_FIFO_URUN_INT) |
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COND(enabled, HDMI_AUD_INT_AUD_SAM_DROP_INT));
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hdmi_write(hdmi, REG_HDMI_AUDIO_CFG, audio_config);
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DBG("audio %sabled", enabled ? "en" : "dis");
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return 0;
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}
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int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
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uint32_t num_of_channels, uint32_t channel_allocation,
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uint32_t level_shift, bool down_mix)
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{
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struct hdmi_audio *audio;
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if (!hdmi)
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return -ENXIO;
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audio = &hdmi->audio;
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if (num_of_channels >= ARRAY_SIZE(nchannels))
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return -EINVAL;
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audio->enabled = enabled;
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audio->infoframe.channels = nchannels[num_of_channels];
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audio->infoframe.channel_allocation = channel_allocation;
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audio->infoframe.level_shift_value = level_shift;
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audio->infoframe.downmix_inhibit = down_mix;
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return msm_hdmi_audio_update(hdmi);
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}
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void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate)
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{
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struct hdmi_audio *audio;
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if (!hdmi)
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return;
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audio = &hdmi->audio;
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if ((rate < 0) || (rate >= MSM_HDMI_SAMPLE_RATE_MAX))
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return;
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audio->rate = rate;
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msm_hdmi_audio_update(hdmi);
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}
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