157 lines
4.6 KiB
C
157 lines
4.6 KiB
C
/*
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* Copyright 2016 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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#include "chan.h"
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#include "runl.h"
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#include <core/gpuobj.h>
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#include <subdev/fault.h>
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#include <nvif/class.h>
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const struct nvkm_chan_func
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gm107_chan = {
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.inst = &gf100_chan_inst,
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.userd = &gk104_chan_userd,
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.ramfc = &gk104_chan_ramfc,
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.bind = gk104_chan_bind_inst,
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.unbind = gk104_chan_unbind,
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.start = gk104_chan_start,
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.stop = gk104_chan_stop,
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.preempt = gk110_chan_preempt,
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};
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static void
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gm107_runl_insert_chan(struct nvkm_chan *chan, struct nvkm_memory *memory, u64 offset)
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{
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nvkm_wo32(memory, offset + 0, chan->id);
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nvkm_wo32(memory, offset + 4, chan->inst->addr >> 12);
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}
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const struct nvkm_runl_func
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gm107_runl = {
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.size = 8,
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.update = nv50_runl_update,
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.insert_cgrp = gk110_runl_insert_cgrp,
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.insert_chan = gm107_runl_insert_chan,
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.commit = gk104_runl_commit,
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.wait = nv50_runl_wait,
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.pending = gk104_runl_pending,
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.block = gk104_runl_block,
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.allow = gk104_runl_allow,
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.fault_clear = gk104_runl_fault_clear,
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.preempt_pending = gf100_runl_preempt_pending,
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};
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static const struct nvkm_enum
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gm107_fifo_mmu_fault_engine[] = {
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{ 0x01, "DISPLAY" },
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{ 0x02, "CAPTURE" },
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{ 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
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{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
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{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
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{ 0x06, "SCHED" },
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{ 0x07, "HOST0" },
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{ 0x08, "HOST1" },
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{ 0x09, "HOST2" },
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{ 0x0a, "HOST3" },
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{ 0x0b, "HOST4" },
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{ 0x0c, "HOST5" },
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{ 0x0d, "HOST6" },
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{ 0x0e, "HOST7" },
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{ 0x0f, "HOSTSR" },
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{ 0x13, "PERF" },
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{ 0x17, "PMU" },
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{ 0x18, "PTP" },
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{}
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};
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const struct nvkm_fifo_func_mmu_fault
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gm107_fifo_mmu_fault = {
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.recover = gf100_fifo_mmu_fault_recover,
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.access = gf100_fifo_mmu_fault_access,
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.engine = gm107_fifo_mmu_fault_engine,
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.reason = gk104_fifo_mmu_fault_reason,
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.hubclient = gk104_fifo_mmu_fault_hubclient,
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.gpcclient = gk104_fifo_mmu_fault_gpcclient,
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};
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void
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gm107_fifo_intr_mmu_fault_unit(struct nvkm_fifo *fifo, int unit)
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{
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struct nvkm_device *device = fifo->engine.subdev.device;
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u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
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u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
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u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
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u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
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struct nvkm_fault_data info;
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info.inst = (u64)inst << 12;
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info.addr = ((u64)vahi << 32) | valo;
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info.time = 0;
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info.engine = unit;
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info.valid = 1;
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info.gpc = (type & 0x1f000000) >> 24;
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info.client = (type & 0x00003f00) >> 8;
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info.access = (type & 0x00000080) >> 7;
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info.hub = (type & 0x00000040) >> 6;
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info.reason = (type & 0x0000000f);
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nvkm_fifo_fault(fifo, &info);
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}
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static int
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gm107_fifo_chid_nr(struct nvkm_fifo *fifo)
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{
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return 2048;
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}
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static const struct nvkm_fifo_func
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gm107_fifo = {
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.chid_nr = gm107_fifo_chid_nr,
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.chid_ctor = gk110_fifo_chid_ctor,
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.runq_nr = gf100_fifo_runq_nr,
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.runl_ctor = gk104_fifo_runl_ctor,
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.init = gk104_fifo_init,
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.init_pbdmas = gk104_fifo_init_pbdmas,
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.intr = gk104_fifo_intr,
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.intr_mmu_fault_unit = gm107_fifo_intr_mmu_fault_unit,
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.intr_ctxsw_timeout = gf100_fifo_intr_ctxsw_timeout,
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.mmu_fault = &gm107_fifo_mmu_fault,
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.nonstall = &gf100_fifo_nonstall,
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.runl = &gm107_runl,
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.runq = &gk208_runq,
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.engn = &gk104_engn,
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.engn_ce = &gk104_engn_ce,
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.cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &gk110_cgrp },
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.chan = {{ 0, 0, KEPLER_CHANNEL_GPFIFO_B }, &gm107_chan },
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};
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int
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gm107_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_fifo **pfifo)
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{
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return nvkm_fifo_new_(&gm107_fifo, device, type, inst, pfifo);
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}
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