493 lines
12 KiB
C
493 lines
12 KiB
C
/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include "chan.h"
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#include "chid.h"
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#include "cgrp.h"
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#include "runl.h"
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#include "runq.h"
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#include <core/gpuobj.h>
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#include <subdev/mmu.h>
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#include <nvif/class.h>
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static u32
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gv100_chan_doorbell_handle(struct nvkm_chan *chan)
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{
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return chan->id;
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}
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static int
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gv100_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv)
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{
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const u64 userd = nvkm_memory_addr(chan->userd.mem) + chan->userd.base;
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const u32 limit2 = ilog2(length / 8);
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nvkm_kmap(chan->inst);
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nvkm_wo32(chan->inst, 0x008, lower_32_bits(userd));
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nvkm_wo32(chan->inst, 0x00c, upper_32_bits(userd));
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nvkm_wo32(chan->inst, 0x010, 0x0000face);
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nvkm_wo32(chan->inst, 0x030, 0x7ffff902);
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nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset));
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nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16));
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nvkm_wo32(chan->inst, 0x084, 0x20400000);
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nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm);
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nvkm_wo32(chan->inst, 0x0e4, priv ? 0x00000020 : 0x00000000);
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nvkm_wo32(chan->inst, 0x0e8, chan->id);
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nvkm_wo32(chan->inst, 0x0f4, 0x00001000 | (priv ? 0x00000100 : 0x00000000));
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nvkm_wo32(chan->inst, 0x0f8, 0x10003080);
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nvkm_mo32(chan->inst, 0x218, 0x00000000, 0x00000000);
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nvkm_done(chan->inst);
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return 0;
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}
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const struct nvkm_chan_func_ramfc
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gv100_chan_ramfc = {
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.write = gv100_chan_ramfc_write,
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.devm = 0xfff,
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.priv = true,
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};
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const struct nvkm_chan_func_userd
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gv100_chan_userd = {
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.bar = -1,
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.size = 0x200,
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.clear = gf100_chan_userd_clear,
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};
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static const struct nvkm_chan_func
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gv100_chan = {
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.inst = &gf100_chan_inst,
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.userd = &gv100_chan_userd,
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.ramfc = &gv100_chan_ramfc,
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.bind = gk104_chan_bind_inst,
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.unbind = gk104_chan_unbind,
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.start = gk104_chan_start,
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.stop = gk104_chan_stop,
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.preempt = gk110_chan_preempt,
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.doorbell_handle = gv100_chan_doorbell_handle,
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};
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void
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gv100_ectx_bind(struct nvkm_engn *engn, struct nvkm_cctx *cctx, struct nvkm_chan *chan)
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{
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u64 addr = 0ULL;
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if (cctx) {
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addr = cctx->vctx->vma->addr;
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addr |= 4ULL;
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}
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nvkm_kmap(chan->inst);
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nvkm_wo32(chan->inst, 0x210, lower_32_bits(addr));
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nvkm_wo32(chan->inst, 0x214, upper_32_bits(addr));
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nvkm_mo32(chan->inst, 0x0ac, 0x00010000, cctx ? 0x00010000 : 0x00000000);
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nvkm_done(chan->inst);
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}
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const struct nvkm_engn_func
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gv100_engn = {
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.chsw = gk104_engn_chsw,
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.cxid = gk104_engn_cxid,
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.ctor = gk104_ectx_ctor,
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.bind = gv100_ectx_bind,
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};
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void
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gv100_ectx_ce_bind(struct nvkm_engn *engn, struct nvkm_cctx *cctx, struct nvkm_chan *chan)
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{
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const u64 bar2 = cctx ? nvkm_memory_bar2(cctx->vctx->inst->memory) : 0ULL;
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nvkm_kmap(chan->inst);
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nvkm_wo32(chan->inst, 0x220, lower_32_bits(bar2));
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nvkm_wo32(chan->inst, 0x224, upper_32_bits(bar2));
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nvkm_mo32(chan->inst, 0x0ac, 0x00020000, cctx ? 0x00020000 : 0x00000000);
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nvkm_done(chan->inst);
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}
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int
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gv100_ectx_ce_ctor(struct nvkm_engn *engn, struct nvkm_vctx *vctx)
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{
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if (nvkm_memory_bar2(vctx->inst->memory) == ~0ULL)
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return -EFAULT;
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return 0;
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}
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const struct nvkm_engn_func
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gv100_engn_ce = {
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.chsw = gk104_engn_chsw,
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.cxid = gk104_engn_cxid,
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.ctor = gv100_ectx_ce_ctor,
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.bind = gv100_ectx_ce_bind,
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};
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static bool
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gv100_runq_intr_1_ctxnotvalid(struct nvkm_runq *runq, int chid)
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{
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struct nvkm_fifo *fifo = runq->fifo;
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struct nvkm_device *device = fifo->engine.subdev.device;
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struct nvkm_chan *chan;
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unsigned long flags;
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RUNQ_ERROR(runq, "CTXNOTVALID chid:%d", chid);
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chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags);
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if (WARN_ON_ONCE(!chan))
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return false;
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nvkm_chan_error(chan, true);
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nvkm_chan_put(&chan, flags);
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nvkm_mask(device, 0x0400ac + (runq->id * 0x2000), 0x00030000, 0x00030000);
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nvkm_wr32(device, 0x040148 + (runq->id * 0x2000), 0x80000000);
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return true;
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}
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const struct nvkm_runq_func
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gv100_runq = {
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.init = gk208_runq_init,
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.intr = gk104_runq_intr,
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.intr_0_names = gk104_runq_intr_0_names,
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.intr_1_ctxnotvalid = gv100_runq_intr_1_ctxnotvalid,
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.idle = gk104_runq_idle,
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};
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void
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gv100_runl_preempt(struct nvkm_runl *runl)
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{
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nvkm_wr32(runl->fifo->engine.subdev.device, 0x002638, BIT(runl->id));
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}
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void
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gv100_runl_insert_chan(struct nvkm_chan *chan, struct nvkm_memory *memory, u64 offset)
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{
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const u64 user = nvkm_memory_addr(chan->userd.mem) + chan->userd.base;
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const u64 inst = chan->inst->addr;
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nvkm_wo32(memory, offset + 0x0, lower_32_bits(user) | chan->runq << 1);
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nvkm_wo32(memory, offset + 0x4, upper_32_bits(user));
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nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->id);
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nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst));
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}
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void
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gv100_runl_insert_cgrp(struct nvkm_cgrp *cgrp, struct nvkm_memory *memory, u64 offset)
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{
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nvkm_wo32(memory, offset + 0x0, (128 << 24) | (3 << 16) | 0x00000001);
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nvkm_wo32(memory, offset + 0x4, cgrp->chan_nr);
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nvkm_wo32(memory, offset + 0x8, cgrp->id);
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nvkm_wo32(memory, offset + 0xc, 0x00000000);
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}
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static const struct nvkm_runl_func
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gv100_runl = {
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.runqs = 2,
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.size = 16,
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.update = nv50_runl_update,
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.insert_cgrp = gv100_runl_insert_cgrp,
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.insert_chan = gv100_runl_insert_chan,
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.commit = gk104_runl_commit,
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.wait = nv50_runl_wait,
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.pending = gk104_runl_pending,
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.block = gk104_runl_block,
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.allow = gk104_runl_allow,
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.preempt = gv100_runl_preempt,
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.preempt_pending = gf100_runl_preempt_pending,
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};
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const struct nvkm_enum
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gv100_fifo_mmu_fault_gpcclient[] = {
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{ 0x00, "T1_0" },
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{ 0x01, "T1_1" },
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{ 0x02, "T1_2" },
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{ 0x03, "T1_3" },
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{ 0x04, "T1_4" },
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{ 0x05, "T1_5" },
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{ 0x06, "T1_6" },
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{ 0x07, "T1_7" },
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{ 0x08, "PE_0" },
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{ 0x09, "PE_1" },
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{ 0x0a, "PE_2" },
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{ 0x0b, "PE_3" },
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{ 0x0c, "PE_4" },
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{ 0x0d, "PE_5" },
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{ 0x0e, "PE_6" },
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{ 0x0f, "PE_7" },
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{ 0x10, "RAST" },
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{ 0x11, "GCC" },
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{ 0x12, "GPCCS" },
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{ 0x13, "PROP_0" },
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{ 0x14, "PROP_1" },
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{ 0x15, "PROP_2" },
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{ 0x16, "PROP_3" },
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{ 0x17, "GPM" },
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{ 0x18, "LTP_UTLB_0" },
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{ 0x19, "LTP_UTLB_1" },
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{ 0x1a, "LTP_UTLB_2" },
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{ 0x1b, "LTP_UTLB_3" },
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{ 0x1c, "LTP_UTLB_4" },
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{ 0x1d, "LTP_UTLB_5" },
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{ 0x1e, "LTP_UTLB_6" },
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{ 0x1f, "LTP_UTLB_7" },
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{ 0x20, "RGG_UTLB" },
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{ 0x21, "T1_8" },
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{ 0x22, "T1_9" },
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{ 0x23, "T1_10" },
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{ 0x24, "T1_11" },
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{ 0x25, "T1_12" },
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{ 0x26, "T1_13" },
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{ 0x27, "T1_14" },
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{ 0x28, "T1_15" },
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{ 0x29, "TPCCS_0" },
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{ 0x2a, "TPCCS_1" },
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{ 0x2b, "TPCCS_2" },
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{ 0x2c, "TPCCS_3" },
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{ 0x2d, "TPCCS_4" },
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{ 0x2e, "TPCCS_5" },
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{ 0x2f, "TPCCS_6" },
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{ 0x30, "TPCCS_7" },
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{ 0x31, "PE_8" },
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{ 0x32, "PE_9" },
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{ 0x33, "TPCCS_8" },
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{ 0x34, "TPCCS_9" },
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{ 0x35, "T1_16" },
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{ 0x36, "T1_17" },
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{ 0x37, "T1_18" },
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{ 0x38, "T1_19" },
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{ 0x39, "PE_10" },
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{ 0x3a, "PE_11" },
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{ 0x3b, "TPCCS_10" },
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{ 0x3c, "TPCCS_11" },
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{ 0x3d, "T1_20" },
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{ 0x3e, "T1_21" },
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{ 0x3f, "T1_22" },
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{ 0x40, "T1_23" },
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{ 0x41, "PE_12" },
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{ 0x42, "PE_13" },
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{ 0x43, "TPCCS_12" },
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{ 0x44, "TPCCS_13" },
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{ 0x45, "T1_24" },
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{ 0x46, "T1_25" },
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{ 0x47, "T1_26" },
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{ 0x48, "T1_27" },
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{ 0x49, "PE_14" },
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{ 0x4a, "PE_15" },
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{ 0x4b, "TPCCS_14" },
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{ 0x4c, "TPCCS_15" },
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{ 0x4d, "T1_28" },
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{ 0x4e, "T1_29" },
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{ 0x4f, "T1_30" },
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{ 0x50, "T1_31" },
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{ 0x51, "PE_16" },
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{ 0x52, "PE_17" },
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{ 0x53, "TPCCS_16" },
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{ 0x54, "TPCCS_17" },
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{ 0x55, "T1_32" },
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{ 0x56, "T1_33" },
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{ 0x57, "T1_34" },
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{ 0x58, "T1_35" },
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{ 0x59, "PE_18" },
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{ 0x5a, "PE_19" },
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{ 0x5b, "TPCCS_18" },
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{ 0x5c, "TPCCS_19" },
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{ 0x5d, "T1_36" },
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{ 0x5e, "T1_37" },
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{ 0x5f, "T1_38" },
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{ 0x60, "T1_39" },
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{}
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};
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const struct nvkm_enum
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gv100_fifo_mmu_fault_hubclient[] = {
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{ 0x00, "VIP" },
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{ 0x01, "CE0" },
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{ 0x02, "CE1" },
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{ 0x03, "DNISO" },
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{ 0x04, "FE" },
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{ 0x05, "FECS" },
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{ 0x06, "HOST" },
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{ 0x07, "HOST_CPU" },
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{ 0x08, "HOST_CPU_NB" },
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{ 0x09, "ISO" },
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{ 0x0a, "MMU" },
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{ 0x0b, "NVDEC" },
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{ 0x0d, "NVENC1" },
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{ 0x0e, "NISO" },
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{ 0x0f, "P2P" },
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{ 0x10, "PD" },
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{ 0x11, "PERF" },
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{ 0x12, "PMU" },
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{ 0x13, "RASTERTWOD" },
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{ 0x14, "SCC" },
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{ 0x15, "SCC_NB" },
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{ 0x16, "SEC" },
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{ 0x17, "SSYNC" },
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{ 0x18, "CE2" },
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{ 0x19, "XV" },
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{ 0x1a, "MMU_NB" },
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{ 0x1b, "NVENC0" },
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{ 0x1c, "DFALCON" },
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{ 0x1d, "SKED" },
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{ 0x1e, "AFALCON" },
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{ 0x1f, "DONT_CARE" },
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{ 0x20, "HSCE0" },
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{ 0x21, "HSCE1" },
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{ 0x22, "HSCE2" },
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{ 0x23, "HSCE3" },
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{ 0x24, "HSCE4" },
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{ 0x25, "HSCE5" },
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{ 0x26, "HSCE6" },
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{ 0x27, "HSCE7" },
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{ 0x28, "HSCE8" },
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{ 0x29, "HSCE9" },
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{ 0x2a, "HSHUB" },
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{ 0x2b, "PTP_X0" },
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{ 0x2c, "PTP_X1" },
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{ 0x2d, "PTP_X2" },
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{ 0x2e, "PTP_X3" },
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{ 0x2f, "PTP_X4" },
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{ 0x30, "PTP_X5" },
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{ 0x31, "PTP_X6" },
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{ 0x32, "PTP_X7" },
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{ 0x33, "NVENC2" },
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{ 0x34, "VPR_SCRUBBER0" },
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{ 0x35, "VPR_SCRUBBER1" },
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{ 0x36, "DWBIF" },
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{ 0x37, "FBFALCON" },
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{ 0x38, "CE_SHIM" },
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{ 0x39, "GSP" },
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{}
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};
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const struct nvkm_enum
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gv100_fifo_mmu_fault_reason[] = {
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{ 0x00, "PDE" },
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{ 0x01, "PDE_SIZE" },
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{ 0x02, "PTE" },
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{ 0x03, "VA_LIMIT_VIOLATION" },
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{ 0x04, "UNBOUND_INST_BLOCK" },
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{ 0x05, "PRIV_VIOLATION" },
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{ 0x06, "RO_VIOLATION" },
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{ 0x07, "WO_VIOLATION" },
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{ 0x08, "PITCH_MASK_VIOLATION" },
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{ 0x09, "WORK_CREATION" },
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{ 0x0a, "UNSUPPORTED_APERTURE" },
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{ 0x0b, "COMPRESSION_FAILURE" },
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{ 0x0c, "UNSUPPORTED_KIND" },
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{ 0x0d, "REGION_VIOLATION" },
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{ 0x0e, "POISONED" },
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{ 0x0f, "ATOMIC_VIOLATION" },
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{}
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};
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static const struct nvkm_enum
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gv100_fifo_mmu_fault_engine[] = {
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{ 0x01, "DISPLAY" },
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{ 0x03, "PTP" },
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{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
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{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
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{ 0x06, "PWR_PMU" },
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{ 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
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{ 0x09, "PERF" },
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{ 0x1f, "PHYSICAL" },
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{ 0x20, "HOST0" },
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{ 0x21, "HOST1" },
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{ 0x22, "HOST2" },
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{ 0x23, "HOST3" },
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{ 0x24, "HOST4" },
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{ 0x25, "HOST5" },
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{ 0x26, "HOST6" },
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{ 0x27, "HOST7" },
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{ 0x28, "HOST8" },
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{ 0x29, "HOST9" },
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{ 0x2a, "HOST10" },
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{ 0x2b, "HOST11" },
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{ 0x2c, "HOST12" },
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{ 0x2d, "HOST13" },
|
|
{}
|
|
};
|
|
|
|
const struct nvkm_enum
|
|
gv100_fifo_mmu_fault_access[] = {
|
|
{ 0x0, "VIRT_READ" },
|
|
{ 0x1, "VIRT_WRITE" },
|
|
{ 0x2, "VIRT_ATOMIC" },
|
|
{ 0x3, "VIRT_PREFETCH" },
|
|
{ 0x4, "VIRT_ATOMIC_WEAK" },
|
|
{ 0x8, "PHYS_READ" },
|
|
{ 0x9, "PHYS_WRITE" },
|
|
{ 0xa, "PHYS_ATOMIC" },
|
|
{ 0xb, "PHYS_PREFETCH" },
|
|
{}
|
|
};
|
|
|
|
static const struct nvkm_fifo_func_mmu_fault
|
|
gv100_fifo_mmu_fault = {
|
|
.recover = gf100_fifo_mmu_fault_recover,
|
|
.access = gv100_fifo_mmu_fault_access,
|
|
.engine = gv100_fifo_mmu_fault_engine,
|
|
.reason = gv100_fifo_mmu_fault_reason,
|
|
.hubclient = gv100_fifo_mmu_fault_hubclient,
|
|
.gpcclient = gv100_fifo_mmu_fault_gpcclient,
|
|
};
|
|
|
|
static void
|
|
gv100_fifo_intr_ctxsw_timeout(struct nvkm_fifo *fifo, u32 engm)
|
|
{
|
|
struct nvkm_runl *runl;
|
|
struct nvkm_engn *engn;
|
|
|
|
nvkm_runl_foreach(runl, fifo) {
|
|
nvkm_runl_foreach_engn_cond(engn, runl, engm & BIT(engn->id))
|
|
nvkm_runl_rc_engn(runl, engn);
|
|
}
|
|
}
|
|
|
|
static const struct nvkm_fifo_func
|
|
gv100_fifo = {
|
|
.chid_nr = gm200_fifo_chid_nr,
|
|
.chid_ctor = gk110_fifo_chid_ctor,
|
|
.runq_nr = gm200_fifo_runq_nr,
|
|
.runl_ctor = gk104_fifo_runl_ctor,
|
|
.init = gk104_fifo_init,
|
|
.init_pbdmas = gk104_fifo_init_pbdmas,
|
|
.intr = gk104_fifo_intr,
|
|
.intr_ctxsw_timeout = gv100_fifo_intr_ctxsw_timeout,
|
|
.mmu_fault = &gv100_fifo_mmu_fault,
|
|
.nonstall = &gf100_fifo_nonstall,
|
|
.runl = &gv100_runl,
|
|
.runq = &gv100_runq,
|
|
.engn = &gv100_engn,
|
|
.engn_ce = &gv100_engn_ce,
|
|
.cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &gk110_cgrp, .force = true },
|
|
.chan = {{ 0, 0, VOLTA_CHANNEL_GPFIFO_A }, &gv100_chan },
|
|
};
|
|
|
|
int
|
|
gv100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
|
|
struct nvkm_fifo **pfifo)
|
|
{
|
|
return nvkm_fifo_new_(&gv100_fifo, device, type, inst, pfifo);
|
|
}
|