493 lines
13 KiB
Plaintext
493 lines
13 KiB
Plaintext
/* fuc microcode for gf100 PGRAPH/GPC
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*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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/* TODO
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* - bracket certain functions with scratch writes, useful for debugging
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* - watchdog timer around ctx operations
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*/
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#ifdef INCLUDE_DATA
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gpc_mmio_list_head: .b32 #mmio_list_base
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gpc_mmio_list_tail:
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tpc_mmio_list_head: .b32 #mmio_list_base
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tpc_mmio_list_tail:
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unk_mmio_list_head: .b32 #mmio_list_base
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unk_mmio_list_tail: .b32 #mmio_list_base
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gpc_id: .b32 0
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tpc_count: .b32 0
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tpc_mask: .b32 0
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#if NV_PGRAPH_GPCX_UNK__SIZE > 0
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unk_count: .b32 0
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unk_mask: .b32 0
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#endif
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cmd_queue: queue_init
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mmio_list_base:
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#endif
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#ifdef INCLUDE_CODE
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#define gpc_addr(reg,addr) /*
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*/ imm32(reg,addr) /*
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*/ or reg NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE
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#define gpc_wr32(addr,reg) /*
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*/ gpc_addr($r14,addr) /*
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*/ mov b32 $r15 reg /*
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*/ call(nv_wr32)
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// reports an exception to the host
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//
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// In: $r15 error code (see os.h)
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//
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error:
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push $r14
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nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15)
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mov $r15 1
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nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15)
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pop $r14
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ret
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#if CHIPSET >= GM107
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tpc_strand_wait:
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push $r9
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trace_set(T_STRTPC)
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tpc_strand_busy:
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nv_iord($r9, NV_PGRAPH_GPCX_GPCCS_TPC_STATUS, 0)
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bra b32 $r9 0x0 ne #tpc_strand_busy
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trace_clr(T_STRTPC)
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pop $r9
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ret
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#define tpc_strand_wait() call(tpc_strand_wait)
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#define tpc_strand_enable() /*
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*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_ENABLE /*
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*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*
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*/ tpc_strand_wait()
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#define tpc_strand_disable() /*
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*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_DISABLE /*
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*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*
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*/ tpc_strand_wait()
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#define tpc_strand_seek(p) /*
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*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL /*
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*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15) /*
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*/ mov $r15 p /*
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*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_SELECT, $r15) /*
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*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SEEK /*
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*/ tpc_strand_wait()
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#define tpc_strand_info(m) /*
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*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*
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*/ mov $r15 m /*
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*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_DATA, $r15) /*
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*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_GET_INFO /*
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*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*
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*/ tpc_strand_wait()
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#endif
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// GPC fuc initialisation, executed by triggering ucode start, will
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// fall through to main loop after completion.
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//
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// Input:
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// CC_SCRATCH[1]: context base
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//
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// Output:
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// CC_SCRATCH[0]:
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// 31:31: set to signal completion
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// CC_SCRATCH[1]:
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// 31:0: GPC context size
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//
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init:
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clear b32 $r0
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// setup stack
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nv_iord($r1, NV_PGRAPH_GPCX_GPCCS_CAPS, 0)
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extr $r1 $r1 9:17
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shl b32 $r1 8
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mov $sp $r1
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// enable fifo access
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mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2)
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// setup i0 handler, and route all interrupts to it
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mov $r1 #ih
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mov $iv0 $r1
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0)
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// enable fifo interrupt
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mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2)
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// enable interrupts
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bset $flags ie0
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// how many TPCs do we have?
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nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0)
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mov $r3 1
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and $r2 0x1f
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shl b32 $r3 $r2
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sub b32 $r3 1
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st b32 D[$r0 + #tpc_count] $r2
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st b32 D[$r0 + #tpc_mask] $r3
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// determine which GPC we are, setup (optional) mmio access offset
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nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0)
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st b32 D[$r0 + #gpc_id] $r2
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shl b32 $r2 15
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMIO_BASE, 0, $r2)
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#if NV_PGRAPH_GPCX_UNK__SIZE > 0
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// figure out which, and how many, UNKs are actually present
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gpc_addr($r14, 0x500c30)
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clear b32 $r2
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clear b32 $r3
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clear b32 $r4
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init_unk_loop:
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call(nv_rd32)
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cmp b32 $r15 0
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bra z #init_unk_next
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mov $r15 1
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shl b32 $r15 $r2
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or $r4 $r15
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add b32 $r3 1
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init_unk_next:
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add b32 $r2 1
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add b32 $r14 4
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cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
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bra ne #init_unk_loop
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init_unk_done:
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st b32 D[$r0 + #unk_count] $r3
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st b32 D[$r0 + #unk_mask] $r4
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#endif
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// initialise context base, and size tracking
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nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0)
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clear b32 $r3 // track GPC context size here
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// set mmctx base addresses now so we don't have to do it later,
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// they don't currently ever change
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shr b32 $r5 $r2 8
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5)
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5)
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// calculate GPC mmio context size
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ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
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ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
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call(mmctx_size)
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add b32 $r2 $r15
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add b32 $r3 $r15
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// calculate per-TPC mmio context size
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ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
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ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
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call(mmctx_size)
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ld b32 $r14 D[$r0 + #tpc_count]
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mulu $r14 $r15
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add b32 $r2 $r14
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add b32 $r3 $r14
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#if NV_PGRAPH_GPCX_UNK__SIZE > 0
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// calculate per-UNK mmio context size
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ld b32 $r14 D[$r0 + #unk_mmio_list_head]
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ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
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call(mmctx_size)
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ld b32 $r14 D[$r0 + #unk_count]
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mulu $r14 $r15
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add b32 $r2 $r14
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add b32 $r3 $r14
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#endif
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// round up base/size to 256 byte boundary (for strand SWBASE)
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shr b32 $r3 2
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?!
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shr b32 $r2 8
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shr b32 $r3 6
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add b32 $r2 1
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add b32 $r3 1
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shl b32 $r2 8
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shl b32 $r3 8
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// calculate size of strand context data
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mov b32 $r15 $r2
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call(strand_ctx_init)
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add b32 $r2 $r15
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add b32 $r3 $r15
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#if CHIPSET >= GM107
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// calculate size of tpc strand context data
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mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL
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gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)
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tpc_strand_enable();
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tpc_strand_seek(0);
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tpc_strand_info(-1);
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ld b32 $r4 D[$r0 + #tpc_count]
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gpc_addr($r5, NV_PGRAPH_GPC0_TPC0)
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tpc_strand_init_tpc_loop:
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add b32 $r14 $r5 NV_TPC_STRAND_CNT
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call(nv_rd32)
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mov b32 $r6 $r15
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clear b32 $r7
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tpc_strand_init_idx_loop:
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add b32 $r14 $r5 NV_TPC_STRAND_INDEX
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mov b32 $r15 $r7
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call(nv_wr32)
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add b32 $r14 $r5 NV_TPC_STRAND_SAVE_SWBASE
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shr b32 $r15 $r2 8
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call(nv_wr32)
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add b32 $r14 $r5 NV_TPC_STRAND_LOAD_SWBASE
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shr b32 $r15 $r2 8
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call(nv_wr32)
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add b32 $r14 $r5 NV_TPC_STRAND_WORDS
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call(nv_rd32)
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shr b32 $r15 6
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add b32 $r15 1
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shl b32 $r15 8
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add b32 $r2 $r15
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add b32 $r3 $r15
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add b32 $r7 1
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sub b32 $r6 1
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bra nz #tpc_strand_init_idx_loop
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add b32 $r5 NV_PGRAPH_GPC0_TPC0__SIZE
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sub b32 $r4 1
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bra nz #tpc_strand_init_tpc_loop
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mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL
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gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)
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tpc_strand_disable();
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#endif
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// save context size, and tell HUB we're done
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3)
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clear b32 $r2
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bset $r2 31
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2)
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// Main program loop, very simple, sleeps until woken up by the interrupt
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// handler, pulls a command from the queue and executes its handler
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//
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wait:
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sleep $p0
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bset $flags $p0
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main:
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mov $r13 #cmd_queue
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call(queue_get)
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bra $p1 #wait
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// 0x0000-0x0003 are all context transfers
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cmpu b32 $r14 0x04
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bra nc #main_not_ctx_xfer
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// fetch $flags and mask off $p1/$p2
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mov $r1 $flags
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mov $r2 0x0006
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not b32 $r2
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and $r1 $r2
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// set $p1/$p2 according to transfer type
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shl b32 $r14 1
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or $r1 $r14
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mov $flags $r1
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// transfer context data
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call(ctx_xfer)
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bra #main
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main_not_ctx_xfer:
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shl b32 $r15 $r14 16
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or $r15 E_BAD_COMMAND
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call(error)
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bra #main
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// interrupt handler
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ih:
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push $r0
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push $r8
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mov $r8 $flags
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push $r8
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push $r9
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push $r10
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push $r11
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push $r13
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push $r14
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push $r15
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clear b32 $r0
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// incoming fifo command?
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nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0)
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and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO
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bra e #ih_no_fifo
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// queue incoming fifo command for later processing
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mov $r13 #cmd_queue
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nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0)
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nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0)
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call(queue_put)
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mov $r14 1
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14)
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// ack, and wake up main()
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ih_no_fifo:
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10)
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pop $r15
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pop $r14
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pop $r13
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pop $r11
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pop $r10
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pop $r9
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pop $r8
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mov $flags $r8
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pop $r8
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pop $r0
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bclr $flags $p0
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iret
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// Set this GPC's bit in HUB_BAR, used to signal completion of various
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// activities to the HUB fuc
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//
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hub_barrier_done:
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mov $r15 1
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ld b32 $r14 D[$r0 + #gpc_id]
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shl b32 $r15 $r14
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nv_wr32(0x409418, $r15) // 0x409418 - HUB_BAR_SET
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ret
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// Disables various things, waits a bit, and re-enables them..
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//
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// Not sure how exactly this helps, perhaps "ENABLE" is not such a
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// good description for the bits we turn off? Anyways, without this,
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// funny things happen.
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//
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ctx_redswitch:
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mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
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mov $r14 8
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ctx_redswitch_delay:
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sub b32 $r14 1
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bra ne #ctx_redswitch_delay
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or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11
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or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15)
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ret
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// Transfer GPC context data between GPU and storage area
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//
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// In: $r15 context base address
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// $p1 clear on save, set on load
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// $p2 set if opposite direction done/will be done, so:
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// on save it means: "a load will follow this save"
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// on load it means: "a save preceeded this load"
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//
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ctx_xfer:
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// set context base address
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15)
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#if CHIPSET >= GM107
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gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_MEM_BASE, $r15)
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#endif
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bra not $p1 #ctx_xfer_not_load
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call(ctx_redswitch)
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ctx_xfer_not_load:
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// strands
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call(strand_pre)
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clear b32 $r2
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2)
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xbit $r2 $flags $p1 // SAVE/LOAD
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add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE
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nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2)
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#if CHIPSET >= GM107
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tpc_strand_enable();
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tpc_strand_seek(0);
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xbit $r15 $flags $p1 // SAVE/LOAD
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add b32 $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SAVE
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gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)
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#endif
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// mmio context
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xbit $r10 $flags $p1 // direction
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or $r10 2 // first
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imm32($r11,0x500000)
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ld b32 $r12 D[$r0 + #gpc_id]
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shl b32 $r12 15
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add b32 $r11 $r12 // base = NV_PGRAPH_GPCn
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ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
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ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
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mov $r14 0 // not multi
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call(mmctx_xfer)
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// per-TPC mmio context
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xbit $r10 $flags $p1 // direction
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#if !NV_PGRAPH_GPCX_UNK__SIZE
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or $r10 4 // last
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#endif
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imm32($r11, 0x504000)
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ld b32 $r12 D[$r0 + #gpc_id]
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shl b32 $r12 15
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|
add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0
|
|
ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
|
|
ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
|
|
ld b32 $r15 D[$r0 + #tpc_mask]
|
|
mov $r14 0x800 // stride = 0x800
|
|
call(mmctx_xfer)
|
|
|
|
#if NV_PGRAPH_GPCX_UNK__SIZE > 0
|
|
// per-UNK mmio context
|
|
xbit $r10 $flags $p1 // direction
|
|
or $r10 4 // last
|
|
imm32($r11, 0x503000)
|
|
ld b32 $r12 D[$r0 + #gpc_id]
|
|
shl b32 $r12 15
|
|
add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0
|
|
ld b32 $r12 D[$r0 + #unk_mmio_list_head]
|
|
ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
|
|
ld b32 $r15 D[$r0 + #unk_mask]
|
|
mov $r14 0x200 // stride = 0x200
|
|
call(mmctx_xfer)
|
|
#endif
|
|
|
|
// wait for strands to finish
|
|
call(strand_wait)
|
|
#if CHIPSET >= GM107
|
|
tpc_strand_wait()
|
|
#endif
|
|
|
|
// if load, or a save without a load following, do some
|
|
// unknown stuff that's done after finishing a block of
|
|
// strand commands
|
|
bra $p1 #ctx_xfer_post
|
|
bra not $p2 #ctx_xfer_done
|
|
ctx_xfer_post:
|
|
call(strand_post)
|
|
#if CHIPSET >= GM107
|
|
tpc_strand_disable()
|
|
#endif
|
|
|
|
// mark completion in HUB's barrier
|
|
ctx_xfer_done:
|
|
call(hub_barrier_done)
|
|
ret
|
|
#endif
|