102 lines
2.9 KiB
C
102 lines
2.9 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <core/gpuobj.h>
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#include <core/memory.h>
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#include <subdev/timer.h>
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void
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nvkm_falcon_v1_load_imem(struct nvkm_falcon *falcon, void *data, u32 start,
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u32 size, u16 tag, u8 port, bool secure)
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{
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u8 rem = size % 4;
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u32 reg;
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int i;
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size -= rem;
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reg = start | BIT(24) | (secure ? BIT(28) : 0);
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nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg);
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for (i = 0; i < size / 4; i++) {
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/* write new tag every 256B */
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if ((i & 0x3f) == 0)
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nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++);
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nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]);
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}
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/*
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* If size is not a multiple of 4, mask the last work to ensure garbage
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* does not get written
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*/
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if (rem) {
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u32 extra = ((u32 *)data)[i];
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/* write new tag every 256B */
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if ((i & 0x3f) == 0)
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nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++);
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nvkm_falcon_wr32(falcon, 0x184 + (port * 16),
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extra & (BIT(rem * 8) - 1));
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++i;
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}
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/* code must be padded to 0x40 words */
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for (; i & 0x3f; i++)
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nvkm_falcon_wr32(falcon, 0x184 + (port * 16), 0);
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}
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void
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nvkm_falcon_v1_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start,
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u32 size, u8 port)
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{
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u8 rem = size % 4;
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int i;
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size -= rem;
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nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), start | (0x1 << 24));
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for (i = 0; i < size / 4; i++)
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nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8), ((u32 *)data)[i]);
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/*
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* If size is not a multiple of 4, mask the last word to ensure garbage
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* does not get written
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*/
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if (rem) {
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u32 extra = ((u32 *)data)[i];
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nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8),
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extra & (BIT(rem * 8) - 1));
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}
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}
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void
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nvkm_falcon_v1_start(struct nvkm_falcon *falcon)
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{
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u32 reg = nvkm_falcon_rd32(falcon, 0x100);
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if (reg & BIT(6))
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nvkm_falcon_wr32(falcon, 0x130, 0x2);
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else
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nvkm_falcon_wr32(falcon, 0x100, 0x2);
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}
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