160 lines
5.4 KiB
C
160 lines
5.4 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __NVKM_CLK_GK20A_H__
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#define __NVKM_CLK_GK20A_H__
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#define KHZ (1000)
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#define MHZ (KHZ * 1000)
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#define MASK(w) ((1 << (w)) - 1)
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#define GK20A_CLK_GPC_MDIV 1000
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#define SYS_GPCPLL_CFG_BASE 0x00137000
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#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0)
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#define GPCPLL_CFG_ENABLE BIT(0)
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#define GPCPLL_CFG_IDDQ BIT(1)
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#define GPCPLL_CFG_LOCK_DET_OFF BIT(4)
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#define GPCPLL_CFG_LOCK BIT(17)
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#define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc)
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#define GPCPLL_CFG2_SETUP2_SHIFT 16
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#define GPCPLL_CFG2_PLL_STEPA_SHIFT 24
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#define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18)
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#define GPCPLL_CFG3_VCO_CTRL_SHIFT 0
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#define GPCPLL_CFG3_VCO_CTRL_WIDTH 9
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#define GPCPLL_CFG3_VCO_CTRL_MASK \
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(MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT)
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#define GPCPLL_CFG3_PLL_STEPB_SHIFT 16
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#define GPCPLL_CFG3_PLL_STEPB_WIDTH 8
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#define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4)
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#define GPCPLL_COEFF_M_SHIFT 0
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#define GPCPLL_COEFF_M_WIDTH 8
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#define GPCPLL_COEFF_N_SHIFT 8
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#define GPCPLL_COEFF_N_WIDTH 8
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#define GPCPLL_COEFF_N_MASK \
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(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT)
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#define GPCPLL_COEFF_P_SHIFT 16
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#define GPCPLL_COEFF_P_WIDTH 6
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#define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c)
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#define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0
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#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8
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#define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16
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#define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22
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#define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31
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#define GPC_BCAST_GPCPLL_CFG_BASE 0x00132800
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#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCAST_GPCPLL_CFG_BASE + 0xa0)
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#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24
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#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \
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(0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)
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#define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100)
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#define SEL_VCO_GPC2CLK_OUT_SHIFT 0
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#define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250)
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#define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1
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#define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31
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#define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1
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#define GPC2CLK_OUT_VCODIV_WIDTH 6
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#define GPC2CLK_OUT_VCODIV_SHIFT 8
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#define GPC2CLK_OUT_VCODIV1 0
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#define GPC2CLK_OUT_VCODIV2 2
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#define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
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GPC2CLK_OUT_VCODIV_SHIFT)
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#define GPC2CLK_OUT_BYPDIV_WIDTH 6
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#define GPC2CLK_OUT_BYPDIV_SHIFT 0
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#define GPC2CLK_OUT_BYPDIV31 0x3c
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#define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
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GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\
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| (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
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| (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
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#define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \
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GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \
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| (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \
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| (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT))
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/* All frequencies in Khz */
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struct gk20a_clk_pllg_params {
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u32 min_vco, max_vco;
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u32 min_u, max_u;
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u32 min_m, max_m;
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u32 min_n, max_n;
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u32 min_pl, max_pl;
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};
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struct gk20a_pll {
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u32 m;
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u32 n;
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u32 pl;
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};
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struct gk20a_clk {
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struct nvkm_clk base;
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const struct gk20a_clk_pllg_params *params;
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struct gk20a_pll pll;
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u32 parent_rate;
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u32 (*div_to_pl)(u32);
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u32 (*pl_to_div)(u32);
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};
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#define gk20a_clk(p) container_of((p), struct gk20a_clk, base)
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u32 gk20a_pllg_calc_rate(struct gk20a_clk *, struct gk20a_pll *);
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int gk20a_pllg_calc_mnp(struct gk20a_clk *, unsigned long, struct gk20a_pll *);
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void gk20a_pllg_read_mnp(struct gk20a_clk *, struct gk20a_pll *);
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void gk20a_pllg_write_mnp(struct gk20a_clk *, const struct gk20a_pll *);
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static inline bool
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gk20a_pllg_is_enabled(struct gk20a_clk *clk)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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u32 val;
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val = nvkm_rd32(device, GPCPLL_CFG);
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return val & GPCPLL_CFG_ENABLE;
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}
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static inline u32
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gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll)
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{
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return DIV_ROUND_UP(pll->m * clk->params->min_vco,
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clk->parent_rate / KHZ);
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}
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int gk20a_clk_ctor(struct nvkm_device *, enum nvkm_subdev_type, int, const struct nvkm_clk_func *,
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const struct gk20a_clk_pllg_params *, struct gk20a_clk *);
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void gk20a_clk_fini(struct nvkm_clk *);
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int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src);
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int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *);
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int gk20a_clk_prog(struct nvkm_clk *);
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void gk20a_clk_tidy(struct nvkm_clk *);
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int gk20a_clk_setup_slide(struct gk20a_clk *);
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#endif
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