748 lines
19 KiB
C
748 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (C) 2014 Broadcom Corporation
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#define N_DATA_REGS 8
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/*
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* PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
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* size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per
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* data register whereas STB SoCs use 4 byte per data register transfer,
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* account for this difference in total count per transaction and mask to
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* use.
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*/
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#define BSC_CNT_REG1_MASK(nb) (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0))
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#define BSC_CNT_REG1_SHIFT 0
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/* BSC CTL register field definitions */
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#define BSC_CTL_REG_DTF_MASK 0x00000003
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#define BSC_CTL_REG_SCL_SEL_MASK 0x00000030
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#define BSC_CTL_REG_SCL_SEL_SHIFT 4
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#define BSC_CTL_REG_INT_EN_MASK 0x00000040
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#define BSC_CTL_REG_INT_EN_SHIFT 6
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#define BSC_CTL_REG_DIV_CLK_MASK 0x00000080
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/* BSC_IIC_ENABLE r/w enable and interrupt field definitions */
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#define BSC_IIC_EN_RESTART_MASK 0x00000040
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#define BSC_IIC_EN_NOSTART_MASK 0x00000020
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#define BSC_IIC_EN_NOSTOP_MASK 0x00000010
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#define BSC_IIC_EN_NOACK_MASK 0x00000004
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#define BSC_IIC_EN_INTRP_MASK 0x00000002
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#define BSC_IIC_EN_ENABLE_MASK 0x00000001
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/* BSC_CTLHI control register field definitions */
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#define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK 0x00000080
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#define BSC_CTLHI_REG_DATAREG_SIZE_MASK 0x00000040
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#define BSC_CTLHI_REG_IGNORE_ACK_MASK 0x00000002
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#define BSC_CTLHI_REG_WAIT_DIS_MASK 0x00000001
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#define I2C_TIMEOUT 100 /* msecs */
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/* Condition mask used for non combined transfer */
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#define COND_RESTART BSC_IIC_EN_RESTART_MASK
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#define COND_NOSTART BSC_IIC_EN_NOSTART_MASK
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#define COND_NOSTOP BSC_IIC_EN_NOSTOP_MASK
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#define COND_START_STOP (COND_RESTART | COND_NOSTART | COND_NOSTOP)
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/* BSC data transfer direction */
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#define DTF_WR_MASK 0x00000000
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#define DTF_RD_MASK 0x00000001
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/* BSC data transfer direction combined format */
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#define DTF_RD_WR_MASK 0x00000002
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#define DTF_WR_RD_MASK 0x00000003
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#define INT_ENABLE true
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#define INT_DISABLE false
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/* BSC block register map structure to cache fields to be written */
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struct bsc_regs {
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u32 chip_address; /* slave address */
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u32 data_in[N_DATA_REGS]; /* tx data buffer*/
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u32 cnt_reg; /* rx/tx data length */
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u32 ctl_reg; /* control register */
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u32 iic_enable; /* xfer enable and status */
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u32 data_out[N_DATA_REGS]; /* rx data buffer */
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u32 ctlhi_reg; /* more control fields */
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u32 scl_param; /* reserved */
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};
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struct bsc_clk_param {
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u32 hz;
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u32 scl_mask;
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u32 div_mask;
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};
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enum bsc_xfer_cmd {
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CMD_WR,
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CMD_RD,
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CMD_WR_NOACK,
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CMD_RD_NOACK,
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};
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static char const *cmd_string[] = {
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[CMD_WR] = "WR",
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[CMD_RD] = "RD",
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[CMD_WR_NOACK] = "WR NOACK",
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[CMD_RD_NOACK] = "RD NOACK",
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};
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enum bus_speeds {
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SPD_375K,
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SPD_390K,
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SPD_187K,
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SPD_200K,
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SPD_93K,
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SPD_97K,
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SPD_46K,
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SPD_50K
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};
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static const struct bsc_clk_param bsc_clk[] = {
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[SPD_375K] = {
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.hz = 375000,
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.scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
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.div_mask = 0
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},
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[SPD_390K] = {
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.hz = 390000,
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.scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
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.div_mask = 0
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},
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[SPD_187K] = {
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.hz = 187500,
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.scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
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.div_mask = 0
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},
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[SPD_200K] = {
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.hz = 200000,
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.scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
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.div_mask = 0
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},
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[SPD_93K] = {
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.hz = 93750,
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.scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
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.div_mask = BSC_CTL_REG_DIV_CLK_MASK
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},
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[SPD_97K] = {
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.hz = 97500,
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.scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
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.div_mask = BSC_CTL_REG_DIV_CLK_MASK
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},
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[SPD_46K] = {
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.hz = 46875,
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.scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
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.div_mask = BSC_CTL_REG_DIV_CLK_MASK
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},
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[SPD_50K] = {
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.hz = 50000,
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.scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
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.div_mask = BSC_CTL_REG_DIV_CLK_MASK
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}
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};
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struct brcmstb_i2c_dev {
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struct device *device;
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void __iomem *base;
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int irq;
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struct bsc_regs *bsc_regmap;
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struct i2c_adapter adapter;
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struct completion done;
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u32 clk_freq_hz;
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int data_regsz;
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};
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/* register accessors for both be and le cpu arch */
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define __bsc_readl(_reg) ioread32be(_reg)
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#define __bsc_writel(_val, _reg) iowrite32be(_val, _reg)
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#else
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#define __bsc_readl(_reg) ioread32(_reg)
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#define __bsc_writel(_val, _reg) iowrite32(_val, _reg)
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#endif
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#define bsc_readl(_dev, _reg) \
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__bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg))
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#define bsc_writel(_dev, _val, _reg) \
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__bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
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static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev)
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{
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return (N_DATA_REGS * dev->data_regsz);
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}
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static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev)
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{
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return dev->data_regsz;
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}
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static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev,
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bool int_en)
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{
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if (int_en)
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/* Enable BSC CTL interrupt line */
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dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK;
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else
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/* Disable BSC CTL interrupt line */
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dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK;
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barrier();
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bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
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}
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static irqreturn_t brcmstb_i2c_isr(int irq, void *devid)
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{
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struct brcmstb_i2c_dev *dev = devid;
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u32 status_bsc_ctl = bsc_readl(dev, ctl_reg);
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u32 status_iic_intrp = bsc_readl(dev, iic_enable);
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dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n",
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status_bsc_ctl, status_iic_intrp);
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if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK))
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return IRQ_NONE;
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brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
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complete(&dev->done);
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dev_dbg(dev->device, "isr handled");
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return IRQ_HANDLED;
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}
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/* Wait for device to be ready */
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static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
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while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) {
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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cpu_relax();
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}
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return 0;
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}
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/* i2c xfer completion function, handles both irq and polling mode */
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static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev)
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{
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int ret = 0;
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unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT);
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if (dev->irq >= 0) {
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if (!wait_for_completion_timeout(&dev->done, timeout))
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ret = -ETIMEDOUT;
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} else {
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/* we are in polling mode */
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u32 bsc_intrp;
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unsigned long time_left = jiffies + timeout;
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do {
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bsc_intrp = bsc_readl(dev, iic_enable) &
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BSC_IIC_EN_INTRP_MASK;
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if (time_after(jiffies, time_left)) {
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ret = -ETIMEDOUT;
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break;
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}
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cpu_relax();
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} while (!bsc_intrp);
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}
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if (dev->irq < 0 || ret == -ETIMEDOUT)
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brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
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return ret;
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}
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/* Set xfer START/STOP conditions for subsequent transfer */
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static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev,
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u32 cond_flag)
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{
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u32 regval = dev->bsc_regmap->iic_enable;
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dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag;
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}
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/* Send I2C request check completion */
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static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev,
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enum bsc_xfer_cmd cmd)
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{
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int rc = 0;
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struct bsc_regs *pi2creg = dev->bsc_regmap;
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/* Make sure the hardware is ready */
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rc = brcmstb_i2c_wait_if_busy(dev);
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if (rc < 0)
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return rc;
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/* only if we are in interrupt mode */
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if (dev->irq >= 0)
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reinit_completion(&dev->done);
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/* enable BSC CTL interrupt line */
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brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE);
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/* initiate transfer by setting iic_enable */
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pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK;
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bsc_writel(dev, pi2creg->iic_enable, iic_enable);
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/* Wait for transaction to finish or timeout */
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rc = brcmstb_i2c_wait_for_completion(dev);
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if (rc) {
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dev_dbg(dev->device, "intr timeout for cmd %s\n",
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cmd_string[cmd]);
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goto cmd_out;
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}
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if ((cmd == CMD_RD || cmd == CMD_WR) &&
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bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) {
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rc = -EREMOTEIO;
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dev_dbg(dev->device, "controller received NOACK intr for %s\n",
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cmd_string[cmd]);
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}
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cmd_out:
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bsc_writel(dev, 0, cnt_reg);
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bsc_writel(dev, 0, iic_enable);
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return rc;
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}
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/* Actual data transfer through the BSC master */
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static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
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u8 *buf, unsigned int len,
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struct i2c_msg *pmsg)
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{
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int cnt, byte, i, rc;
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enum bsc_xfer_cmd cmd;
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u32 ctl_reg;
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struct bsc_regs *pi2creg = dev->bsc_regmap;
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int no_ack = pmsg->flags & I2C_M_IGNORE_NAK;
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int data_regsz = brcmstb_i2c_get_data_regsz(dev);
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/* see if the transaction needs to check NACK conditions */
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if (no_ack) {
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cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK
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: CMD_WR_NOACK;
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pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK;
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} else {
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cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR;
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pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK;
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}
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bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg);
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/* set data transfer direction */
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ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK;
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if (cmd == CMD_WR || cmd == CMD_WR_NOACK)
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pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK;
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else
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pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK;
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/* set the read/write length */
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bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) &
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(len << BSC_CNT_REG1_SHIFT), cnt_reg);
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/* Write data into data_in register */
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if (cmd == CMD_WR || cmd == CMD_WR_NOACK) {
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for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
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u32 word = 0;
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for (byte = 0; byte < data_regsz; byte++) {
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word >>= BITS_PER_BYTE;
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if ((cnt + byte) < len)
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word |= buf[cnt + byte] <<
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(BITS_PER_BYTE * (data_regsz - 1));
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}
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bsc_writel(dev, word, data_in[i]);
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}
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}
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/* Initiate xfer, the function will return on completion */
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rc = brcmstb_send_i2c_cmd(dev, cmd);
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if (rc != 0) {
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dev_dbg(dev->device, "%s failure", cmd_string[cmd]);
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return rc;
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}
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/* Read data from data_out register */
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if (cmd == CMD_RD || cmd == CMD_RD_NOACK) {
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for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
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u32 data = bsc_readl(dev, data_out[i]);
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for (byte = 0; byte < data_regsz &&
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(byte + cnt) < len; byte++) {
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buf[cnt + byte] = data & 0xff;
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data >>= BITS_PER_BYTE;
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}
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}
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}
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return 0;
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}
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/* Write a single byte of data to the i2c bus */
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static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev,
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u8 *buf, unsigned int nak_expected)
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{
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enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK;
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bsc_writel(dev, 1, cnt_reg);
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bsc_writel(dev, *buf, data_in);
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return brcmstb_send_i2c_cmd(dev, cmd);
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}
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/* Send i2c address */
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static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev,
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struct i2c_msg *msg)
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{
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unsigned char addr;
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if (msg->flags & I2C_M_TEN) {
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/* First byte is 11110XX0 where XX is upper 2 bits */
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addr = 0xF0 | ((msg->addr & 0x300) >> 7);
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bsc_writel(dev, addr, chip_address);
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/* Second byte is the remaining 8 bits */
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addr = msg->addr & 0xFF;
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if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
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return -EREMOTEIO;
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if (msg->flags & I2C_M_RD) {
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/* For read, send restart without stop condition */
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brcmstb_set_i2c_start_stop(dev, COND_RESTART
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| COND_NOSTOP);
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/* Then re-send the first byte with the read bit set */
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addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
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if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
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return -EREMOTEIO;
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}
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} else {
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addr = i2c_8bit_addr_from_msg(msg);
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bsc_writel(dev, addr, chip_address);
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}
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return 0;
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}
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/* Master transfer function */
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static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
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struct i2c_msg msgs[], int num)
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{
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struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter);
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struct i2c_msg *pmsg;
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int rc = 0;
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int i;
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int bytes_to_xfer;
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u8 *tmp_buf;
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int len = 0;
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int xfersz = brcmstb_i2c_get_xfersz(dev);
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u32 cond, cond_per_msg;
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/* Loop through all messages */
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for (i = 0; i < num; i++) {
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pmsg = &msgs[i];
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len = pmsg->len;
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tmp_buf = pmsg->buf;
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dev_dbg(dev->device,
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"msg# %d/%d flg %x buf %x len %d\n", i,
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num - 1, pmsg->flags,
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pmsg->buf ? pmsg->buf[0] : '0', pmsg->len);
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|
|
|
if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART))
|
|
cond = ~COND_START_STOP;
|
|
else
|
|
cond = COND_RESTART | COND_NOSTOP;
|
|
|
|
brcmstb_set_i2c_start_stop(dev, cond);
|
|
|
|
/* Send slave address */
|
|
if (!(pmsg->flags & I2C_M_NOSTART)) {
|
|
rc = brcmstb_i2c_do_addr(dev, pmsg);
|
|
if (rc < 0) {
|
|
dev_dbg(dev->device,
|
|
"NACK for addr %2.2x msg#%d rc = %d\n",
|
|
pmsg->addr, i, rc);
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
cond_per_msg = cond;
|
|
|
|
/* Perform data transfer */
|
|
while (len) {
|
|
bytes_to_xfer = min(len, xfersz);
|
|
|
|
if (len <= xfersz) {
|
|
if (i == (num - 1))
|
|
cond_per_msg = cond_per_msg &
|
|
~(COND_RESTART | COND_NOSTOP);
|
|
else
|
|
cond_per_msg = cond;
|
|
} else {
|
|
cond_per_msg = (cond_per_msg & ~COND_RESTART) |
|
|
COND_NOSTOP;
|
|
}
|
|
|
|
brcmstb_set_i2c_start_stop(dev, cond_per_msg);
|
|
|
|
rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf,
|
|
bytes_to_xfer, pmsg);
|
|
if (rc < 0)
|
|
goto out;
|
|
|
|
len -= bytes_to_xfer;
|
|
tmp_buf += bytes_to_xfer;
|
|
|
|
cond_per_msg = COND_NOSTART | COND_NOSTOP;
|
|
}
|
|
}
|
|
|
|
rc = num;
|
|
out:
|
|
return rc;
|
|
|
|
}
|
|
|
|
static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR
|
|
| I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING;
|
|
}
|
|
|
|
static const struct i2c_algorithm brcmstb_i2c_algo = {
|
|
.master_xfer = brcmstb_i2c_xfer,
|
|
.functionality = brcmstb_i2c_functionality,
|
|
};
|
|
|
|
static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev)
|
|
{
|
|
int i = 0, num_speeds = ARRAY_SIZE(bsc_clk);
|
|
u32 clk_freq_hz = dev->clk_freq_hz;
|
|
|
|
for (i = 0; i < num_speeds; i++) {
|
|
if (bsc_clk[i].hz == clk_freq_hz) {
|
|
dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK
|
|
| BSC_CTL_REG_DIV_CLK_MASK);
|
|
dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask |
|
|
bsc_clk[i].div_mask);
|
|
bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* in case we did not get find a valid speed */
|
|
if (i == num_speeds) {
|
|
i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >>
|
|
BSC_CTL_REG_SCL_SEL_SHIFT;
|
|
dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n",
|
|
bsc_clk[i].hz);
|
|
}
|
|
}
|
|
|
|
static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev)
|
|
{
|
|
if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32))
|
|
/* set 4 byte data in/out xfers */
|
|
dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;
|
|
else
|
|
dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK;
|
|
|
|
bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg);
|
|
/* set bus speed */
|
|
brcmstb_i2c_set_bus_speed(dev);
|
|
}
|
|
|
|
#define AUTOI2C_CTRL0 0x26c
|
|
#define AUTOI2C_CTRL0_RELEASE_BSC BIT(1)
|
|
|
|
static int bcm2711_release_bsc(struct brcmstb_i2c_dev *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev->device);
|
|
struct resource *iomem;
|
|
void __iomem *autoi2c;
|
|
|
|
/* Map hardware registers */
|
|
iomem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "auto-i2c");
|
|
autoi2c = devm_ioremap_resource(&pdev->dev, iomem);
|
|
if (IS_ERR(autoi2c))
|
|
return PTR_ERR(autoi2c);
|
|
|
|
writel(AUTOI2C_CTRL0_RELEASE_BSC, autoi2c + AUTOI2C_CTRL0);
|
|
devm_iounmap(&pdev->dev, autoi2c);
|
|
|
|
/* We need to reset the controller after the release */
|
|
dev->bsc_regmap->iic_enable = 0;
|
|
bsc_writel(dev, dev->bsc_regmap->iic_enable, iic_enable);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int brcmstb_i2c_probe(struct platform_device *pdev)
|
|
{
|
|
int rc = 0;
|
|
struct brcmstb_i2c_dev *dev;
|
|
struct i2c_adapter *adap;
|
|
struct resource *iomem;
|
|
const char *int_name;
|
|
|
|
/* Allocate memory for private data structure */
|
|
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
|
|
if (!dev)
|
|
return -ENOMEM;
|
|
|
|
dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(*dev->bsc_regmap), GFP_KERNEL);
|
|
if (!dev->bsc_regmap)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, dev);
|
|
dev->device = &pdev->dev;
|
|
init_completion(&dev->done);
|
|
|
|
/* Map hardware registers */
|
|
iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
dev->base = devm_ioremap_resource(dev->device, iomem);
|
|
if (IS_ERR(dev->base)) {
|
|
rc = -ENOMEM;
|
|
goto probe_errorout;
|
|
}
|
|
|
|
if (of_device_is_compatible(dev->device->of_node,
|
|
"brcm,bcm2711-hdmi-i2c")) {
|
|
rc = bcm2711_release_bsc(dev);
|
|
if (rc)
|
|
goto probe_errorout;
|
|
}
|
|
|
|
rc = of_property_read_string(dev->device->of_node, "interrupt-names",
|
|
&int_name);
|
|
if (rc < 0)
|
|
int_name = NULL;
|
|
|
|
/* Get the interrupt number */
|
|
dev->irq = platform_get_irq_optional(pdev, 0);
|
|
|
|
/* disable the bsc interrupt line */
|
|
brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
|
|
|
|
/* register the ISR handler */
|
|
if (dev->irq >= 0) {
|
|
rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,
|
|
IRQF_SHARED,
|
|
int_name ? int_name : pdev->name,
|
|
dev);
|
|
|
|
if (rc) {
|
|
dev_dbg(dev->device, "falling back to polling mode");
|
|
dev->irq = -1;
|
|
}
|
|
}
|
|
|
|
if (of_property_read_u32(dev->device->of_node,
|
|
"clock-frequency", &dev->clk_freq_hz)) {
|
|
dev_warn(dev->device, "setting clock-frequency@%dHz\n",
|
|
bsc_clk[0].hz);
|
|
dev->clk_freq_hz = bsc_clk[0].hz;
|
|
}
|
|
|
|
/* set the data in/out register size for compatible SoCs */
|
|
if (of_device_is_compatible(dev->device->of_node,
|
|
"brcm,brcmper-i2c"))
|
|
dev->data_regsz = sizeof(u8);
|
|
else
|
|
dev->data_regsz = sizeof(u32);
|
|
|
|
brcmstb_i2c_set_bsc_reg_defaults(dev);
|
|
|
|
/* Add the i2c adapter */
|
|
adap = &dev->adapter;
|
|
i2c_set_adapdata(adap, dev);
|
|
adap->owner = THIS_MODULE;
|
|
strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
|
|
adap->algo = &brcmstb_i2c_algo;
|
|
adap->dev.parent = &pdev->dev;
|
|
adap->dev.of_node = pdev->dev.of_node;
|
|
rc = i2c_add_adapter(adap);
|
|
if (rc)
|
|
goto probe_errorout;
|
|
|
|
dev_info(dev->device, "%s@%dhz registered in %s mode\n",
|
|
int_name ? int_name : " ", dev->clk_freq_hz,
|
|
(dev->irq >= 0) ? "interrupt" : "polling");
|
|
|
|
return 0;
|
|
|
|
probe_errorout:
|
|
return rc;
|
|
}
|
|
|
|
static int brcmstb_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev);
|
|
|
|
i2c_del_adapter(&dev->adapter);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int brcmstb_i2c_suspend(struct device *dev)
|
|
{
|
|
struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
|
|
|
|
i2c_mark_adapter_suspended(&i2c_dev->adapter);
|
|
return 0;
|
|
}
|
|
|
|
static int brcmstb_i2c_resume(struct device *dev)
|
|
{
|
|
struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
|
|
|
|
brcmstb_i2c_set_bsc_reg_defaults(i2c_dev);
|
|
i2c_mark_adapter_resumed(&i2c_dev->adapter);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend,
|
|
brcmstb_i2c_resume);
|
|
|
|
static const struct of_device_id brcmstb_i2c_of_match[] = {
|
|
{.compatible = "brcm,brcmstb-i2c"},
|
|
{.compatible = "brcm,brcmper-i2c"},
|
|
{.compatible = "brcm,bcm2711-hdmi-i2c"},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match);
|
|
|
|
static struct platform_driver brcmstb_i2c_driver = {
|
|
.driver = {
|
|
.name = "brcmstb-i2c",
|
|
.of_match_table = brcmstb_i2c_of_match,
|
|
.pm = &brcmstb_i2c_pm,
|
|
},
|
|
.probe = brcmstb_i2c_probe,
|
|
.remove = brcmstb_i2c_remove,
|
|
};
|
|
module_platform_driver(brcmstb_i2c_driver);
|
|
|
|
MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>");
|
|
MODULE_DESCRIPTION("Broadcom Settop I2C Driver");
|
|
MODULE_LICENSE("GPL v2");
|